onur
152 lines
6.1 KiB
Systemverilog
152 lines
6.1 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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// Users can define 'PRINTF_COND' to add an extra gate to prints.
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`ifndef PRINTF_COND_
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`ifdef PRINTF_COND
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`define PRINTF_COND_ (`PRINTF_COND)
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`else // PRINTF_COND
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`define PRINTF_COND_ 1
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`endif // PRINTF_COND
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`endif // not def PRINTF_COND_
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module TLFragmenter_FPGAUART(
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input clock,
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reset,
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output auto_anon_in_a_ready,
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input auto_anon_in_a_valid,
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input [2:0] auto_anon_in_a_bits_opcode,
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auto_anon_in_a_bits_size,
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input [1:0] auto_anon_in_a_bits_source,
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input [28:0] auto_anon_in_a_bits_address,
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input [7:0] auto_anon_in_a_bits_mask,
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input [63:0] auto_anon_in_a_bits_data,
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input auto_anon_in_d_ready,
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output auto_anon_in_d_valid,
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output [2:0] auto_anon_in_d_bits_opcode,
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auto_anon_in_d_bits_size,
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output [1:0] auto_anon_in_d_bits_source,
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output [63:0] auto_anon_in_d_bits_data,
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input auto_anon_out_a_ready,
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output auto_anon_out_a_valid,
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output [2:0] auto_anon_out_a_bits_opcode,
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output [1:0] auto_anon_out_a_bits_size,
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output [5:0] auto_anon_out_a_bits_source,
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output [28:0] auto_anon_out_a_bits_address,
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output [7:0] auto_anon_out_a_bits_mask,
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output [63:0] auto_anon_out_a_bits_data,
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output auto_anon_out_d_ready,
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input auto_anon_out_d_valid,
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input [2:0] auto_anon_out_d_bits_opcode,
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input [1:0] auto_anon_out_d_bits_size,
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input [5:0] auto_anon_out_d_bits_source,
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input [63:0] auto_anon_out_d_bits_data
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);
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wire _repeater_io_full;
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wire _repeater_io_deq_valid;
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wire [2:0] _repeater_io_deq_bits_opcode;
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wire [2:0] _repeater_io_deq_bits_size;
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wire [1:0] _repeater_io_deq_bits_source;
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wire [28:0] _repeater_io_deq_bits_address;
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wire [7:0] _repeater_io_deq_bits_mask;
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reg [2:0] acknum;
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reg [2:0] dOrig;
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reg dToggle;
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wire dFirst = acknum == 3'h0;
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wire [5:0] _dsizeOH1_T = 6'h7 << auto_anon_out_d_bits_size;
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wire [2:0] _GEN = ~(auto_anon_out_d_bits_source[2:0]);
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wire [2:0] dFirst_size_hi = auto_anon_out_d_bits_source[2:0] & {1'h1, _GEN[2:1]};
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wire [2:0] _dFirst_size_T_8 =
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{1'h0, dFirst_size_hi[2:1]} | ~(_dsizeOH1_T[2:0]) & {_GEN[0], _dsizeOH1_T[2:1]};
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wire [2:0] dFirst_size =
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{|dFirst_size_hi,
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|(_dFirst_size_T_8[2:1]),
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_dFirst_size_T_8[2] | _dFirst_size_T_8[0]};
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wire drop =
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~(auto_anon_out_d_bits_opcode[0]) & (|(auto_anon_out_d_bits_source[2:0]));
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wire anonOut_d_ready = auto_anon_in_d_ready | drop;
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wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size;
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reg [2:0] gennum;
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wire aFirst = gennum == 3'h0;
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wire [2:0] aFragnum = aFirst ? ~(_aOrigOH1_T[5:3]) : gennum - 3'h1;
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reg aToggle_r;
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wire _GEN_0 = ~_repeater_io_full | _repeater_io_deq_bits_opcode[2];
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wire _GEN_1 = ~_repeater_io_full | (&_repeater_io_deq_bits_mask);
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`ifndef SYNTHESIS
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always @(posedge clock) begin
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if ((`PRINTF_COND_) & ~reset & ~_GEN_0)
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$fwrite(32'h80000002,
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"Assertion failed\n at Fragmenter.scala:321 assert (!repeater.io.full || !aHasData)\n");
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if ((`PRINTF_COND_) & ~reset & ~_GEN_1)
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$fwrite(32'h80000002,
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"Assertion failed\n at Fragmenter.scala:324 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n");
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end // always @(posedge)
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`endif // not def SYNTHESIS
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always @(posedge clock) begin
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automatic logic _GEN_2;
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automatic logic _GEN_3;
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_GEN_2 = anonOut_d_ready & auto_anon_out_d_valid;
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_GEN_3 = _GEN_2 & dFirst;
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if (~reset) begin
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end
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if (reset) begin
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acknum <= 3'h0;
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dToggle <= 1'h0;
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gennum <= 3'h0;
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end
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else begin
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if (_GEN_2)
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acknum <=
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dFirst
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? auto_anon_out_d_bits_source[2:0]
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: acknum
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- {2'h0, auto_anon_out_d_bits_opcode[0] | (&auto_anon_out_d_bits_size)};
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if (_GEN_3)
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dToggle <= auto_anon_out_d_bits_source[3];
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if (auto_anon_out_a_ready & _repeater_io_deq_valid)
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gennum <= aFragnum;
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end
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if (_GEN_3)
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dOrig <= dFirst_size;
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if (aFirst)
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aToggle_r <= dToggle;
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end // always @(posedge)
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Repeater_TLBundleA_a29d64s2k1z3u repeater (
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.clock (clock),
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.reset (reset),
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.io_repeat (_repeater_io_deq_bits_opcode[2] & (|aFragnum)),
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.io_full (_repeater_io_full),
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.io_enq_ready (auto_anon_in_a_ready),
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.io_enq_valid (auto_anon_in_a_valid),
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.io_enq_bits_opcode (auto_anon_in_a_bits_opcode),
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.io_enq_bits_size (auto_anon_in_a_bits_size),
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.io_enq_bits_source (auto_anon_in_a_bits_source),
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.io_enq_bits_address (auto_anon_in_a_bits_address),
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.io_enq_bits_mask (auto_anon_in_a_bits_mask),
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.io_deq_ready (auto_anon_out_a_ready),
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.io_deq_valid (_repeater_io_deq_valid),
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.io_deq_bits_opcode (_repeater_io_deq_bits_opcode),
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.io_deq_bits_size (_repeater_io_deq_bits_size),
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.io_deq_bits_source (_repeater_io_deq_bits_source),
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.io_deq_bits_address (_repeater_io_deq_bits_address),
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.io_deq_bits_mask (_repeater_io_deq_bits_mask)
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);
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assign auto_anon_in_d_valid = auto_anon_out_d_valid & ~drop;
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assign auto_anon_in_d_bits_opcode = auto_anon_out_d_bits_opcode;
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assign auto_anon_in_d_bits_size = dFirst ? dFirst_size : dOrig;
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assign auto_anon_in_d_bits_source = auto_anon_out_d_bits_source[5:4];
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assign auto_anon_in_d_bits_data = auto_anon_out_d_bits_data;
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assign auto_anon_out_a_valid = _repeater_io_deq_valid;
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assign auto_anon_out_a_bits_opcode = _repeater_io_deq_bits_opcode;
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assign auto_anon_out_a_bits_size =
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_repeater_io_deq_bits_size[2] ? 2'h3 : _repeater_io_deq_bits_size[1:0];
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assign auto_anon_out_a_bits_source =
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{_repeater_io_deq_bits_source, ~(aFirst ? dToggle : aToggle_r), aFragnum};
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assign auto_anon_out_a_bits_address =
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{_repeater_io_deq_bits_address[28:6],
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_repeater_io_deq_bits_address[5:0] | {~(aFragnum | _aOrigOH1_T[5:3]), 3'h0}};
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assign auto_anon_out_a_bits_mask = _repeater_io_full ? 8'hFF : auto_anon_in_a_bits_mask;
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assign auto_anon_out_a_bits_data = auto_anon_in_a_bits_data;
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assign auto_anon_out_d_ready = anonOut_d_ready;
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endmodule
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