55 lines
1.7 KiB
Markdown
55 lines
1.7 KiB
Markdown
# Hardware Layout
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Quick map for the hardware flow:
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```text
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upstream/rocket-chip/src/
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Required upstream Rocket-Chip Scala sources and Verilog/C++ resources used by
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the generator and simulation helpers.
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upstream/rocket-chip/bootrom/
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Required upstream default BootROM image/source for upstream configs. The
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project VCU118 flow uses soc/software/bootloader for the SPI flash boot path.
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upstream/rocket-chip/scala
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upstream/rocket-chip/resources
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Short symlink views for browsing upstream Scala and resource files inside
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upstream/rocket-chip/src.
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soc/scala/
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Project-specific Rocket SoC Chisel/Scala layer. Mill adds this directory to
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the rocketchip module sources through build.sc.
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generated/
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FIRRTL and SystemVerilog dump area:
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- generated/vcu118-soc/
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- generated/vcu118-soc-verilog/
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- generated/asic-rocket-soc/
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- generated/asic-rocket-soc-verilog/
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- generated/asic-rocket-soc-sim-verilog/
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fpga/vcu118/rtl/
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Hand-written VCU118 shell/helper RTL that Vivado reads in addition to the
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generated Rocket SystemVerilog.
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fpga/vcu118/constraints/
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VCU118 XDC constraints.
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sim/asic/rocket/
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ASIC testbench, behavioral models, and wave.do.
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sim/fpga/vcu118/
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FPGA smoke/sim entry point.
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external/gps/rtl/
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GPS RTL sources and filelist consumed by FPGA and ASIC flows. FPGA Makefiles
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pass this path as the default GPS_SYSTEM_DIR, so the Vivado flow does not
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depend on a user-specific /home/... checkout.
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```
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GPS tracking olcum yolunun 20 ms Doppler/C/N0 snapshot, PCLK synchronizer,
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APB register/interrupt ve software velocity WLS sozlesmesi
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`external/gps/rtl/trck_src/README.md` icinde belgelenir. PPS PI periferigi,
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runtime coefficient/lock register map'i ve fiziksel pin sinirlari
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`external/gps/rtl/pps/README.md` icindedir.
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