227 lines
12 KiB
Plaintext
227 lines
12 KiB
Plaintext
# Efinity Interface Configuration for the Ti375C529 development kit.
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# Pin assignments follow the kit user guide and the Efinity 2025.2 device DB.
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# Board I/O bank voltages. Keep these aligned with the Efinix out-of-box
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# Ti375C529 development-kit project.
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design.set_device_property("2A", "DYNAMIC_VOLTAGE", "0", "IOBANK")
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design.set_mode_sel_name("2A", "2A_MODE_SEL", "2A")
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design.set_device_property("2A", "VOLTAGE", "1.8", "IOBANK")
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design.set_device_property("2B", "DYNAMIC_VOLTAGE", "0", "IOBANK")
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design.set_mode_sel_name("2B", "2B_MODE_SEL", "2B")
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design.set_device_property("2B", "VOLTAGE", "1.8", "IOBANK")
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design.set_device_property("2C", "DYNAMIC_VOLTAGE", "0", "IOBANK")
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design.set_mode_sel_name("2C", "2C_MODE_SEL", "2C")
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design.set_device_property("2C", "VOLTAGE", "1.8", "IOBANK")
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design.set_device_property("2D", "DYNAMIC_VOLTAGE", "0", "IOBANK")
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design.set_mode_sel_name("2D", "2D_MODE_SEL", "2D")
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design.set_device_property("2D", "VOLTAGE", "1.8", "IOBANK")
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design.set_device_property("2E", "DYNAMIC_VOLTAGE", "0", "IOBANK")
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design.set_mode_sel_name("2E", "2E_MODE_SEL", "2E")
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design.set_device_property("2E", "VOLTAGE", "1.8", "IOBANK")
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design.set_device_property("4A_4B", "DYNAMIC_VOLTAGE", "0", "IOBANK")
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design.set_mode_sel_name("4A_4B", "4A_4B_MODE_SEL", "4A_4B")
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design.set_device_property("4A_4B", "VOLTAGE", "1.8", "IOBANK")
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design.set_device_property("4C", "DYNAMIC_VOLTAGE", "0", "IOBANK")
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design.set_mode_sel_name("4C", "4C_MODE_SEL", "4C")
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design.set_device_property("4C", "VOLTAGE", "1.8", "IOBANK")
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design.set_device_property("4D", "DYNAMIC_VOLTAGE", "0", "IOBANK")
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design.set_mode_sel_name("4D", "4D_MODE_SEL", "4D")
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design.set_device_property("4D", "VOLTAGE", "1.8", "IOBANK")
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design.set_device_property("BL2_BL3", "DYNAMIC_VOLTAGE", "0", "IOBANK")
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design.set_mode_sel_name("BL2_BL3", "BL2_MODE_SEL", "BL2")
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design.set_mode_sel_name("BL2_BL3", "BL3_MODE_SEL", "BL3")
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design.set_device_property("BL2_BL3", "VOLTAGE", "3.3", "IOBANK")
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design.set_device_property("BR0", "DYNAMIC_VOLTAGE", "0", "IOBANK")
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design.set_mode_sel_name("BR0", "BR0_MODE_SEL", "BR0")
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design.set_device_property("BR0", "VOLTAGE", "3.3", "IOBANK")
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design.set_device_property("BR3_BR4", "DYNAMIC_VOLTAGE", "0", "IOBANK")
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design.set_mode_sel_name("BR3_BR4", "BR3_MODE_SEL", "BR3")
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design.set_mode_sel_name("BR3_BR4", "BR4_MODE_SEL", "BR4")
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design.set_device_property("BR3_BR4", "VOLTAGE", "3.3", "IOBANK")
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design.set_device_property("TL1_TL5", "DYNAMIC_VOLTAGE", "0", "IOBANK")
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design.set_mode_sel_name("TL1_TL5", "TL1_MODE_SEL", "TL1")
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design.set_mode_sel_name("TL1_TL5", "TL5_MODE_SEL", "TL5")
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design.set_device_property("TL1_TL5", "VOLTAGE", "3.3", "IOBANK")
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design.set_device_property("TR0", "DYNAMIC_VOLTAGE", "0", "IOBANK")
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design.set_mode_sel_name("TR0", "TR0_MODE_SEL", "TR0")
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design.set_device_property("TR0", "VOLTAGE", "3.3", "IOBANK")
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design.set_device_property("TR1", "DYNAMIC_VOLTAGE", "0", "IOBANK")
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design.set_mode_sel_name("TR1", "TR1_MODE_SEL", "TR1")
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design.set_device_property("TR1", "VOLTAGE", "3.3", "IOBANK")
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design.set_device_property("TR2", "DYNAMIC_VOLTAGE", "0", "IOBANK")
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design.set_mode_sel_name("TR2", "TR2_MODE_SEL", "TR2")
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design.set_device_property("TR2", "VOLTAGE", "3.3", "IOBANK")
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# External GPIO.
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design.create_input_gpio("reset_n")
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design.set_property("reset_n", "PULL_OPTION", "WEAK_PULLUP")
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design.create_input_gpio("uart_rx")
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design.create_output_gpio("uart_tx")
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# Lower 512-Mbit configuration flash. After active configuration completes,
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# these dedicated SPI pins become fabric GPIO and are driven by Rocket's MMIO
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# SPI controller so the BootROM can read the application region.
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design.create_output_gpio("flash_sck")
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design.create_output_gpio("flash_csn")
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design.create_inout_gpio("flash_dq", 3, 0)
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# The AX2771 sample clock is routed to J13 pin 10 / GPIOR_95_CLK12 so it
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# enters the fabric through a dedicated global-clock input instead of being
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# promoted from normal GPIO routing by the placer.
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design.create_input_clock_gpio("rf_clk")
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design.create_input_gpio("rf_data", 3, 0)
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design.create_output_gpio("pmod_spi_sck")
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design.create_output_gpio("pmod_spi_csn")
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design.create_inout_gpio("pmod_spi_dq", 3, 0)
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design.create_input_gpio("pmod_irq")
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design.create_output_gpio("gps_pps")
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design.create_output_gpio("led", 4, 0)
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# The two PMOD headers, FTDI UART, reset switch, 100 MHz oscillator, and
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# LED9/LED10 use the development kit's 3.3 V banks. GPIOs otherwise default
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# to 1.8 V LVCMOS, so state these assignments explicitly.
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design.set_property("reset_n", "IO_STANDARD", "3.3_V_LVCMOS")
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design.set_property("uart_rx", "IO_STANDARD", "3.3_V_LVCMOS")
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design.set_property("uart_tx", "IO_STANDARD", "3.3_V_LVCMOS")
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design.set_property("flash_sck", "IO_STANDARD", "1.8_V_LVCMOS")
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design.set_property("flash_csn", "IO_STANDARD", "1.8_V_LVCMOS")
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design.set_property("flash_dq[0]", "IO_STANDARD", "1.8_V_LVCMOS")
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design.set_property("flash_dq[1]", "IO_STANDARD", "1.8_V_LVCMOS")
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design.set_property("flash_dq[2]", "IO_STANDARD", "1.8_V_LVCMOS")
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design.set_property("flash_dq[3]", "IO_STANDARD", "1.8_V_LVCMOS")
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design.set_property("flash_csn", "PULL_OPTION", "WEAK_PULLUP")
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design.set_property("flash_dq[0]", "PULL_OPTION", "WEAK_PULLUP")
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design.set_property("flash_dq[1]", "PULL_OPTION", "WEAK_PULLUP")
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design.set_property("flash_dq[2]", "PULL_OPTION", "WEAK_PULLUP")
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design.set_property("flash_dq[3]", "PULL_OPTION", "WEAK_PULLUP")
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design.set_property("rf_clk", "IO_STANDARD", "3.3_V_LVCMOS")
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design.set_property("rf_data[0]", "IO_STANDARD", "3.3_V_LVCMOS")
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design.set_property("rf_data[1]", "IO_STANDARD", "3.3_V_LVCMOS")
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design.set_property("rf_data[2]", "IO_STANDARD", "3.3_V_LVCMOS")
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design.set_property("rf_data[3]", "IO_STANDARD", "3.3_V_LVCMOS")
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design.set_property("pmod_spi_sck", "IO_STANDARD", "3.3_V_LVCMOS")
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design.set_property("pmod_spi_csn", "IO_STANDARD", "3.3_V_LVCMOS")
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design.set_property("pmod_spi_dq[0]", "IO_STANDARD", "3.3_V_LVCMOS")
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design.set_property("pmod_spi_dq[1]", "IO_STANDARD", "3.3_V_LVCMOS")
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design.set_property("pmod_spi_dq[2]", "IO_STANDARD", "3.3_V_LVCMOS")
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design.set_property("pmod_spi_dq[3]", "IO_STANDARD", "3.3_V_LVCMOS")
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design.set_property("pmod_irq", "IO_STANDARD", "3.3_V_LVCMOS")
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design.set_property("gps_pps", "IO_STANDARD", "3.3_V_LVCMOS")
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design.set_property("led[0]", "IO_STANDARD", "3.3_V_LVCMOS")
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design.set_property("led[1]", "IO_STANDARD", "3.3_V_LVCMOS")
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# Rocket/fabric clock: 100 MHz board oscillator -> 100 MHz GCLK.
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design.create_block("fabric_pll", "PLL")
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design.gen_pll_ref_clock("fabric_pll", pll_res="PLL_BL0", refclk_src="EXTERNAL", refclk_name="board_clk_100", ext_refclk_no="1")
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design.set_property("board_clk_100", "IO_STANDARD", "3.3_V_LVCMOS")
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design.set_property("fabric_pll", "REFCLK_FREQ", "100", "PLL")
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design.set_property("fabric_pll", "CLKOUT0_PIN", "fabric_clk", "PLL")
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design.set_property("fabric_pll", "CLKOUT0_CONN_TYPE", "gclk", "PLL")
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design.set_property("fabric_pll", "LOCKED_PIN", "fabric_pll_locked", "PLL")
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design.auto_calc_pll_clock("fabric_pll", {"CLKOUT0_FREQ": "100.0", "CLKOUT0_PHASE": "0"})
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# RF-coherent GPS processing clocks. The AX2771's 16.367981 MHz clock enters
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# the fabric on J13 pin 10 / A12 (GPIOR_95_CLK12) and drives the same two-stage
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# clock chain used by the Xilinx targets:
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# RF -> ~55.55556 MHz -> 100 MHz acquisition / 125 MHz tracking.
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design.create_block("gps_ref_pll", "PLL")
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design.gen_pll_ref_clock("gps_ref_pll", pll_res="PLL_TR0", refclk_src="CORE")
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design.set_property("gps_ref_pll", "CORE_CLK_PIN", "rf_clk", "PLL")
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design.set_property("gps_ref_pll", "REFCLK_FREQ", "16.367981", "PLL")
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design.set_property("gps_ref_pll", "CLKOUT1_EN", "1", "PLL")
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design.set_property("gps_ref_pll", "CLKOUT0_PIN", "gps_ref_clk_gen", "PLL")
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design.set_property("gps_ref_pll", "CLKOUT0_CONN_TYPE", "gclk", "PLL")
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design.set_property("gps_ref_pll", "CLKOUT1_PIN", "gps_ref_feedback", "PLL")
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design.set_property("gps_ref_pll", "CLKOUT1_CONN_TYPE", "gclk", "PLL")
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design.set_property("gps_ref_pll", "LOCKED_PIN", "gps_ref_pll_locked", "PLL")
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design.set_property("gps_ref_pll", "FEEDBACK_MODE", "LOCAL", "PLL")
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design.set_property("gps_ref_pll", "FEEDBACK_CLK", "CLK1", "PLL")
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design.set_property("gps_ref_pll", "FRACTIONAL_MODE_EN", "1", "PLL")
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design.set_property("gps_ref_pll", "FRACTIONAL_COEFFICIENT", "10715375", "PLL")
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design.set_property("gps_ref_pll", "M", "4", "PLL")
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design.set_property("gps_ref_pll", "N", "1", "PLL")
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design.set_property("gps_ref_pll", "O", "1", "PLL")
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design.set_property("gps_ref_pll", "CLKOUT0_DIV", "42", "PLL")
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design.set_property("gps_ref_pll", "CLKOUT1_DIV", "35", "PLL")
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design.set_property("gps_ref_pll", "CLKOUT1_PDIV", "5", "PLL")
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design.set_property("gps_ref_pll", "CLKOUT1_SDIV", "30", "PLL")
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design.calc_pll_clock("gps_ref_pll")
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design.create_block("gps_domain_pll", "PLL")
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design.gen_pll_ref_clock("gps_domain_pll", pll_res="PLL_TR1", refclk_src="CORE")
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design.set_property("gps_domain_pll", "CORE_CLK_PIN", "gps_ref_clk_gen", "PLL")
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design.set_property("gps_domain_pll", "REFCLK_FREQ", "55.55555593", "PLL")
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design.set_property("gps_domain_pll", "CLKOUT3_EN", "1", "PLL")
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design.set_property("gps_domain_pll", "CLKOUT4_EN", "1", "PLL")
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design.set_property("gps_domain_pll", "CLKOUT0_PIN", "gps_domain_feedback", "PLL")
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design.set_property("gps_domain_pll", "CLKOUT0_CONN_TYPE", "gclk", "PLL")
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design.set_property("gps_domain_pll", "CLKOUT3_PIN", "gps_acq_clk_gen", "PLL")
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design.set_property("gps_domain_pll", "CLKOUT3_CONN_TYPE", "gclk", "PLL")
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design.set_property("gps_domain_pll", "CLKOUT4_PIN", "gps_trck_clk_gen", "PLL")
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design.set_property("gps_domain_pll", "CLKOUT4_CONN_TYPE", "gclk", "PLL")
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design.set_property("gps_domain_pll", "LOCKED_PIN", "gps_domain_pll_locked", "PLL")
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design.set_property("gps_domain_pll", "FEEDBACK_MODE", "LOCAL", "PLL")
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design.set_property("gps_domain_pll", "FEEDBACK_CLK", "CLK0", "PLL")
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design.set_property("gps_domain_pll", "M", "2", "PLL")
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design.set_property("gps_domain_pll", "N", "1", "PLL")
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design.set_property("gps_domain_pll", "O", "2", "PLL")
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design.set_property("gps_domain_pll", "CLKOUT0_DIV", "18", "PLL")
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design.set_property("gps_domain_pll", "CLKOUT3_DIV", "20", "PLL")
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design.set_property("gps_domain_pll", "CLKOUT4_DIV", "16", "PLL")
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design.calc_pll_clock("gps_domain_pll")
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# Hard JTAG USER1 exposes the TAP handshake at the FPGA core boundary.
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design.create_block("rocket_jtag", "JTAG")
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design.set_property("rocket_jtag", "NAME", "rocket_jtag", "JTAG")
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design.set_property("rocket_jtag", "RESOURCE", "JTAG_USER1", "JTAG")
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design.set_property("rocket_jtag", "CAPTURE", "jtag_CAPTURE", "JTAG")
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design.set_property("rocket_jtag", "DRCK", "jtag_DRCK", "JTAG")
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design.set_property("rocket_jtag", "RESET", "jtag_RESET", "JTAG")
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design.set_property("rocket_jtag", "RUNTEST", "jtag_RUNTEST", "JTAG")
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design.set_property("rocket_jtag", "SEL", "jtag_SEL", "JTAG")
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design.set_property("rocket_jtag", "SHIFT", "jtag_SHIFT", "JTAG")
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design.set_property("rocket_jtag", "TCK", "jtag_TCK", "JTAG")
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design.set_property("rocket_jtag", "TDI", "jtag_TDI", "JTAG")
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design.set_property("rocket_jtag", "TMS", "jtag_TMS", "JTAG")
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design.set_property("rocket_jtag", "UPDATE", "jtag_UPDATE", "JTAG")
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design.set_property("rocket_jtag", "TDO", "jtag_TDO", "JTAG")
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design.assign_resource("rocket_jtag", "JTAG_USER1", "JTAG")
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# Package assignments.
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design.assign_pkg_pin("board_clk_100", "U4")
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design.assign_pkg_pin("reset_n", "U19")
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design.assign_pkg_pin("uart_rx", "E10")
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design.assign_pkg_pin("uart_tx", "E9")
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# Lower configuration flash U47: CDI0..3, CCK, and SSL_N. These assignments
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# match Efinix's Ti375C529 JTAG-to-SPI loader reference design.
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design.assign_pkg_pin("flash_dq[0]", "H4")
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design.assign_pkg_pin("flash_dq[1]", "H5")
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design.assign_pkg_pin("flash_dq[2]", "G5")
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design.assign_pkg_pin("flash_dq[3]", "B7")
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design.assign_pkg_pin("flash_sck", "G6")
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design.assign_pkg_pin("flash_csn", "A7")
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# PMOD0/J13 RF input. J13 pin 10 is the header's dedicated GCLK-capable pin;
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# J13 pin 1 / G15 is intentionally unused.
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design.assign_pkg_pin("rf_clk", "A12")
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design.assign_pkg_pin("rf_data[0]", "G16")
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design.assign_pkg_pin("rf_data[1]", "F16")
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design.assign_pkg_pin("rf_data[2]", "F17")
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design.assign_pkg_pin("rf_data[3]", "G17")
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# PMOD1/J14 SPI + interrupt + PPS.
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design.assign_pkg_pin("pmod_spi_csn", "B12")
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design.assign_pkg_pin("pmod_spi_dq[0]", "C14")
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design.assign_pkg_pin("pmod_spi_dq[1]", "C13")
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design.assign_pkg_pin("pmod_spi_sck", "C12")
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design.assign_pkg_pin("pmod_spi_dq[2]", "D12")
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design.assign_pkg_pin("pmod_spi_dq[3]", "F12")
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design.assign_pkg_pin("pmod_irq", "D13")
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design.assign_pkg_pin("gps_pps", "E13")
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# User LEDs LED9..LED13.
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design.assign_pkg_pin("led[0]", "V4")
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design.assign_pkg_pin("led[1]", "U6")
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design.assign_pkg_pin("led[2]", "L18")
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design.assign_pkg_pin("led[3]", "R20")
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design.assign_pkg_pin("led[4]", "E19")
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