49 lines
2.2 KiB
Tcl
49 lines
2.2 KiB
Tcl
## Digilent Genesys 2 Rev. H, xc7k325tffg900-2.
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## Pins are taken from Digilent Genesys-2-Master.xdc.
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set_property PACKAGE_PIN AD12 [get_ports sysclk_p]
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set_property PACKAGE_PIN AD11 [get_ports sysclk_n]
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set_property IOSTANDARD LVDS [get_ports {sysclk_p sysclk_n}]
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create_clock -period 5.000 -name sysclk_200 [get_ports sysclk_p]
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# Async clock groups and optional RF pins are mode-dependent.
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# build.tcl reads the matching companion XDC and applies clock groups after synth.
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set_property PACKAGE_PIN R19 [get_ports cpu_resetn]
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set_property IOSTANDARD LVCMOS33 [get_ports cpu_resetn]
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# UART is routed through PMOD JB.
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# uart_rx_out is FPGA UART TX on JB[0], uart_tx_in is FPGA UART RX on JB[1].
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# Previous onboard USB-UART pins:
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set_property PACKAGE_PIN Y20 [get_ports uart_tx_in]
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set_property PACKAGE_PIN Y23 [get_ports uart_rx_out]
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#set_property PACKAGE_PIN V30 [get_ports uart_tx_in]
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#set_property PACKAGE_PIN V29 [get_ports uart_rx_out]
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set_property IOSTANDARD LVCMOS33 [get_ports {uart_tx_in uart_rx_out}]
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set_property DRIVE 8 [get_ports uart_rx_out]
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set_property PACKAGE_PIN T28 [get_ports {led[0]}]
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set_property PACKAGE_PIN V19 [get_ports {led[1]}]
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set_property PACKAGE_PIN U30 [get_ports {led[2]}]
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set_property PACKAGE_PIN U29 [get_ports {led[3]}]
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set_property PACKAGE_PIN V20 [get_ports {led[4]}]
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set_property PACKAGE_PIN V26 [get_ports {led[5]}]
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set_property PACKAGE_PIN W24 [get_ports {led[6]}]
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set_property PACKAGE_PIN W23 [get_ports {led[7]}]
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set_property IOSTANDARD LVCMOS33 [get_ports led[*]]
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set_property DRIVE 8 [get_ports led[*]]
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set_property PACKAGE_PIN U19 [get_ports qspi_csn]
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set_property PACKAGE_PIN P24 [get_ports {qspi_d[0]}]
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set_property PACKAGE_PIN R25 [get_ports {qspi_d[1]}]
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set_property PACKAGE_PIN R20 [get_ports {qspi_d[2]}]
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set_property PACKAGE_PIN R21 [get_ports {qspi_d[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {qspi_csn qspi_d[*]}]
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set_property DRIVE 8 [get_ports {qspi_csn qspi_d[*]}]
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set_property SLEW SLOW [get_ports {qspi_csn qspi_d[*]}]
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
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set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
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