79 lines
3.9 KiB
Plaintext
79 lines
3.9 KiB
Plaintext
#-----------------------------------------------------------
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# Vivado v2025.2 (64-bit)
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# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
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# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
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# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
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# Start of session at: Sat Jul 11 20:07:29 2026
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# Process ID : 365586
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# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
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# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_fpga.tcl
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# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.log
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# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/program_fpga.jou
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# Running On : onur
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# Platform : Ubuntu
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# Operating System : Ubuntu 22.04.5 LTS
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# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
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# CPU Frequency : 4199.924 MHz
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# CPU Physical cores : 12
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# CPU Logical cores : 12
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# Host memory : 22112 MB
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# Swap memory : 2147 MB
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# Total Virtual : 24260 MB
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# Available Virtual : 21531 MB
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#-----------------------------------------------------------
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Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
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Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
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source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/program_fpga.tcl
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# set script_dir [file dirname [file normalize [info script]]]
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# set fpga_dir [file normalize [file join $script_dir ../..]]
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# proc getenv_default {name default} {
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# if {[info exists ::env($name)] && $::env($name) ne ""} {
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# return $::env($name)
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# }
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# return $default
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# }
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# set bit_file [file normalize [getenv_default BIT_FILE [file join $fpga_dir out bitstream genesys2_rocket.bit]]]
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# set device_pattern [getenv_default HW_DEVICE_PATTERN xc7k325t*]
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# open_hw_manager
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# connect_hw_server
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INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
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INFO: [Labtools 27-2222] Launching hw_server...
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INFO: [Labtools 27-2221] Launch Output:
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****** Xilinx hw_server v2025.2
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**** Build date : Oct 28 2025 at 16:07:00
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** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:0
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INFO: [Labtools 27-3417] Launching cs_server...
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INFO: [Labtools 27-2221] Launch Output:
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******** Xilinx cs_server v2025.2.0
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****** Build date : Nov 14 2025-02:16:52
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**** Build number : 2025.2.1763075812
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** Copyright 2017-2022 Xilinx, Inc. All Rights Reserved.
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** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
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# open_hw_target
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INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/200300BB2D80B
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# set dev [lindex [get_hw_devices $device_pattern] 0]
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# if {$dev eq ""} {
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# error "No hardware device found matching $device_pattern"
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# }
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# current_hw_device $dev
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# refresh_hw_device $dev
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INFO: [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported soft debug core(s) in it.
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# set_property PROGRAM.FILE $bit_file $dev
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# program_hw_devices $dev
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INFO: [Labtools 27-3164] End of startup status: HIGH
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program_hw_devices: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1669.160 ; gain = 1.000 ; free physical = 9122 ; free virtual = 20028
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# refresh_hw_device $dev
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INFO: [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported soft debug core(s) in it.
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# puts "Programmed FPGA with $bit_file"
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Programmed FPGA with /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
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INFO: [Common 17-206] Exiting Vivado at Sat Jul 11 20:07:44 2026...
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