onur
19 lines
686 B
Systemverilog
19 lines
686 B
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module ClockGroupAggregator_cbus(
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input auto_in_member_cbus_1_clock,
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auto_in_member_cbus_1_reset,
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auto_in_member_cbus_0_clock,
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auto_in_member_cbus_0_reset,
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output auto_out_1_member_pbus_0_clock,
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auto_out_1_member_pbus_0_reset,
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auto_out_0_member_cbus_0_clock,
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auto_out_0_member_cbus_0_reset
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);
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assign auto_out_1_member_pbus_0_clock = auto_in_member_cbus_1_clock;
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assign auto_out_1_member_pbus_0_reset = auto_in_member_cbus_1_reset;
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assign auto_out_0_member_cbus_0_clock = auto_in_member_cbus_0_clock;
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assign auto_out_0_member_cbus_0_reset = auto_in_member_cbus_0_reset;
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endmodule
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