onur
36 lines
1.4 KiB
Systemverilog
36 lines
1.4 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
|
|
module CompareRecFN(
|
|
input [64:0] io_a,
|
|
io_b,
|
|
input io_signaling,
|
|
output io_lt,
|
|
io_eq,
|
|
output [4:0] io_exceptionFlags
|
|
);
|
|
|
|
wire _rawA_out_sig_T = |(io_a[63:61]);
|
|
wire rawA_isSpecial = &(io_a[63:62]);
|
|
wire rawA_isNaN = rawA_isSpecial & io_a[61];
|
|
wire _rawB_out_sig_T = |(io_b[63:61]);
|
|
wire rawB_isSpecial = &(io_b[63:62]);
|
|
wire rawB_isNaN = rawB_isSpecial & io_b[61];
|
|
wire ordered = ~rawA_isNaN & ~rawB_isNaN;
|
|
wire bothInfs = rawA_isSpecial & ~(io_a[61]) & rawB_isSpecial & ~(io_b[61]);
|
|
wire bothZeros = ~_rawA_out_sig_T & ~_rawB_out_sig_T;
|
|
wire eqExps = io_a[63:52] == io_b[63:52];
|
|
wire [52:0] _GEN = {_rawA_out_sig_T, io_a[51:0]};
|
|
wire [52:0] _GEN_0 = {_rawB_out_sig_T, io_b[51:0]};
|
|
wire common_ltMags =
|
|
$signed({1'h0, io_a[63:52]}) < $signed({1'h0, io_b[63:52]}) | eqExps & _GEN < _GEN_0;
|
|
wire common_eqMags = eqExps & _GEN == _GEN_0;
|
|
assign io_lt =
|
|
ordered & ~bothZeros
|
|
& (io_a[64] & ~(io_b[64]) | ~bothInfs
|
|
& (io_a[64] & ~common_ltMags & ~common_eqMags | ~(io_b[64]) & common_ltMags));
|
|
assign io_eq =
|
|
ordered & (bothZeros | io_a[64] == io_b[64] & (bothInfs | common_eqMags));
|
|
assign io_exceptionFlags =
|
|
{rawA_isNaN & ~(io_a[51]) | rawB_isNaN & ~(io_b[51]) | io_signaling & ~ordered, 4'h0};
|
|
endmodule
|
|
|