onur
17 lines
296 B
Systemverilog
17 lines
296 B
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module IntSyncCrossingSource_n1x1(
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input clock,
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reset,
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auto_in_0,
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output auto_out_sync_0
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);
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AsyncResetRegVec_w1_i0 reg_0 (
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.clock (clock),
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.reset (reset),
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.io_d (auto_in_0),
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.io_q (auto_out_sync_0)
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);
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endmodule
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