onur
70 lines
2.4 KiB
Systemverilog
70 lines
2.4 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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// Users can define 'PRINTF_COND' to add an extra gate to prints.
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`ifndef PRINTF_COND_
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`ifdef PRINTF_COND
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`define PRINTF_COND_ (`PRINTF_COND)
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`else // PRINTF_COND
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`define PRINTF_COND_ 1
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`endif // PRINTF_COND
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`endif // not def PRINTF_COND_
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module TLError_1(
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input clock,
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reset,
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output auto_in_a_ready,
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input auto_in_a_valid,
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input [2:0] auto_in_a_bits_opcode,
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input auto_in_d_ready,
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output auto_in_d_valid,
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output [2:0] auto_in_d_bits_opcode,
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output auto_in_d_bits_denied,
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auto_in_d_bits_corrupt
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);
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wire da_ready;
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wire [2:0] da_bits_opcode;
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wire [7:0][2:0] _GEN = '{3'h4, 3'h4, 3'h2, 3'h1, 3'h1, 3'h1, 3'h0, 3'h0};
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reg idle;
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reg r_counter;
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wire _GEN_0 = idle | ~r_counter;
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wire da_valid = auto_in_a_valid & idle;
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assign da_bits_opcode = _GEN[auto_in_a_bits_opcode];
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reg beatsLeft;
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`ifndef SYNTHESIS
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always @(posedge clock) begin
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if ((`PRINTF_COND_) & ~reset & ~_GEN_0)
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$fwrite(32'h80000002,
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"Assertion failed\n at Error.scala:34 assert (idle || da_first) // we only send Grant, never GrantData => simplified flow control below\n");
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end // always @(posedge)
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`endif // not def SYNTHESIS
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reg state_1;
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wire muxState_1 = beatsLeft ? state_1 : da_valid;
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assign da_ready = auto_in_d_ready & (~beatsLeft | state_1);
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wire nodeIn_d_valid = (~beatsLeft | state_1) & da_valid;
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always @(posedge clock) begin
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if (reset) begin
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idle <= 1'h1;
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r_counter <= 1'h0;
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beatsLeft <= 1'h0;
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state_1 <= 1'h0;
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end
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else begin
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automatic logic r_3 = da_ready & da_valid;
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idle <= ~(r_3 & da_bits_opcode == 3'h4) & idle;
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r_counter <= (~r_3 | r_counter - 1'h1) & r_counter;
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beatsLeft <=
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~(~beatsLeft & auto_in_d_ready) & beatsLeft - (auto_in_d_ready & nodeIn_d_valid);
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if (beatsLeft) begin
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end
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else
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state_1 <= da_valid;
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end
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end // always @(posedge)
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assign auto_in_a_ready = da_ready & idle;
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assign auto_in_d_valid = nodeIn_d_valid;
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assign auto_in_d_bits_opcode = muxState_1 ? da_bits_opcode : 3'h0;
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assign auto_in_d_bits_denied = muxState_1;
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assign auto_in_d_bits_corrupt = muxState_1 & da_bits_opcode[0];
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endmodule
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