onur
31 lines
662 B
Systemverilog
31 lines
662 B
Systemverilog
// Generated by CIRCT firtool-1.151.0
|
|
module AsyncResetRegVec_w1_i0(
|
|
input clock,
|
|
reset,
|
|
io_d,
|
|
output io_q
|
|
);
|
|
|
|
reg reg_0;
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset)
|
|
reg_0 <= 1'h0;
|
|
else
|
|
reg_0 <= io_d;
|
|
end // always @(posedge, posedge)
|
|
`ifdef ENABLE_INITIAL_REG_
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif // FIRRTL_BEFORE_INITIAL
|
|
initial begin
|
|
if (reset)
|
|
reg_0 = 1'h0;
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif // FIRRTL_AFTER_INITIAL
|
|
`endif // ENABLE_INITIAL_REG_
|
|
assign io_q = reg_0;
|
|
endmodule
|
|
|