onur
31 lines
692 B
Systemverilog
31 lines
692 B
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module AsyncResetRegVec_w2_i0(
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input clock,
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reset,
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input [1:0] io_d,
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output [1:0] io_q
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);
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reg [1:0] reg_0;
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always @(posedge clock or posedge reset) begin
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if (reset)
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reg_0 <= 2'h0;
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else
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reg_0 <= io_d;
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end // always @(posedge, posedge)
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`ifdef ENABLE_INITIAL_REG_
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`ifdef FIRRTL_BEFORE_INITIAL
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`FIRRTL_BEFORE_INITIAL
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`endif // FIRRTL_BEFORE_INITIAL
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initial begin
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if (reset)
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reg_0 = 2'h0;
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end // initial
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`ifdef FIRRTL_AFTER_INITIAL
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`FIRRTL_AFTER_INITIAL
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`endif // FIRRTL_AFTER_INITIAL
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`endif // ENABLE_INITIAL_REG_
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assign io_q = reg_0;
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endmodule
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