gps/hardware/generated/genesys2-soc-verilog/ICache.sv

// Generated by CIRCT firtool-1.151.0

// Users can define 'PRINTF_COND' to add an extra gate to prints.
`ifndef PRINTF_COND_
  `ifdef PRINTF_COND
    `define PRINTF_COND_ (`PRINTF_COND)
  `else  // PRINTF_COND
    `define PRINTF_COND_ 1
  `endif // PRINTF_COND
`endif // not def PRINTF_COND_
module ICache(
  input         clock,
                reset,
                auto_master_out_a_ready,
  output        auto_master_out_a_valid,
  output [31:0] auto_master_out_a_bits_address,
  output        auto_master_out_a_bits_user_amba_prot_readalloc,
                auto_master_out_a_bits_user_amba_prot_writealloc,
  input         auto_master_out_d_valid,
  input  [2:0]  auto_master_out_d_bits_opcode,
  input  [3:0]  auto_master_out_d_bits_size,
  input  [63:0] auto_master_out_d_bits_data,
  input         auto_master_out_d_bits_corrupt,
                io_req_valid,
  input  [32:0] io_req_bits_addr,
  input  [31:0] io_s1_paddr,
  input         io_s1_kill,
                io_s2_kill,
                io_s2_cacheable,
  output        io_resp_valid,
  output [31:0] io_resp_bits_data,
  output        io_resp_bits_ae,
  input         io_invalidate
);

  wire        rockettile_icache_data_arrays_1_dout_1_en;
  wire        wen_1;
  wire        rockettile_icache_data_arrays_0_dout_en;
  wire        wen;
  wire        rockettile_icache_tag_array_tag_rdata_en;
  wire [5:0]  rockettile_icache_tag_array_tag_rdata_addr;
  wire        io_req_ready;
  wire [31:0] _rockettile_icache_data_arrays_1_ext_RW0_rdata;
  wire [31:0] _rockettile_icache_data_arrays_0_ext_RW0_rdata;
  wire [20:0] _rockettile_icache_tag_array_ext_RW0_rdata;
  wire        s0_valid = io_req_ready & io_req_valid;
  reg         s1_valid;
  reg         s2_valid;
  reg         s2_hit;
  reg         invalidated;
  reg         refill_valid;
  wire        s2_miss = s2_valid & ~s2_hit & ~io_s2_kill;
  reg         s2_request_refill_REG;
  wire        s2_request_refill = s2_miss & s2_request_refill_REG;
  reg  [31:0] refill_paddr;
  wire        refill_one_beat =
    auto_master_out_d_valid & auto_master_out_d_bits_opcode[0];
  assign io_req_ready = ~refill_one_beat;
  wire [26:0] _r_beats1_decode_T = 27'hFFF << auto_master_out_d_bits_size;
  wire [8:0]  r_beats1 =
    auto_master_out_d_bits_opcode[0] ? ~(_r_beats1_decode_T[11:3]) : 9'h0;
  reg  [8:0]  r_counter;
  wire [8:0]  _r_counter1_T = r_counter - 9'h1;
  wire [8:0]  refill_cnt = r_beats1 & ~_r_counter1_T;
  wire        refill_done = refill_one_beat & (r_counter == 9'h1 | r_beats1 == 9'h0);
  assign rockettile_icache_tag_array_tag_rdata_addr = io_req_bits_addr[11:6];
  assign rockettile_icache_tag_array_tag_rdata_en = ~refill_done & s0_valid;
  reg         accruedRefillError;
  wire        refillError =
    auto_master_out_d_bits_corrupt | (|refill_cnt) & accruedRefillError;
  reg  [63:0] vb_array;
  assign wen = refill_one_beat & ~invalidated;
  wire [8:0]  _mem_idx_T_6 = {refill_paddr[11:6], 3'h0};
  assign rockettile_icache_data_arrays_0_dout_en =
    ~wen & s0_valid & ~(io_req_bits_addr[2]);
  assign wen_1 = refill_one_beat & ~invalidated;
  assign rockettile_icache_data_arrays_1_dout_1_en =
    ~wen_1 & s0_valid & io_req_bits_addr[2];
  reg  [31:0] s2_dout_0;
  reg         s2_tl_error;
  always @(posedge clock) begin
    automatic logic        _s1_can_request_refill_T = s2_miss | refill_valid;
    automatic logic [63:0] _s1_vb_T_1 = vb_array >> io_s1_paddr[11:6];
    automatic logic        tagMatch;
    tagMatch =
      _s1_vb_T_1[0]
      & _rockettile_icache_tag_array_ext_RW0_rdata[19:0] == io_s1_paddr[31:12];
    if (reset) begin
      s1_valid <= 1'h0;
      s2_valid <= 1'h0;
      refill_valid <= 1'h0;
      r_counter <= 9'h0;
      vb_array <= 64'h0;
    end
    else begin
      s1_valid <= s0_valid;
      s2_valid <= s1_valid & ~io_s1_kill;
      refill_valid <=
        ~refill_done & (auto_master_out_a_ready & s2_request_refill | refill_valid);
      if (auto_master_out_d_valid)
        r_counter <= r_counter == 9'h0 ? r_beats1 : _r_counter1_T;
      if (io_invalidate)
        vb_array <= 64'h0;
      else if (refill_one_beat) begin
        automatic logic [127:0] _vb_array_T_3 = 128'h1 << refill_paddr[11:6];
        vb_array <=
          refill_done & ~invalidated
            ? vb_array | _vb_array_T_3[63:0]
            : ~(~vb_array | _vb_array_T_3[63:0]);
      end
    end
    s2_hit <= tagMatch;
    invalidated <= refill_valid & (io_invalidate | invalidated);
    s2_request_refill_REG <= ~_s1_can_request_refill_T;
    if (s1_valid & ~_s1_can_request_refill_T)
      refill_paddr <= io_s1_paddr;
    if (refill_one_beat)
      accruedRefillError <= refillError;
    if (s1_valid) begin
      s2_dout_0 <=
        io_s1_paddr[2]
          ? _rockettile_icache_data_arrays_1_ext_RW0_rdata
          : _rockettile_icache_data_arrays_0_ext_RW0_rdata;
      s2_tl_error <= tagMatch & _rockettile_icache_tag_array_ext_RW0_rdata[20];
    end
  end // always @(posedge)
  rockettile_icache_tag_array_64x21 rockettile_icache_tag_array_ext (
    .RW0_addr
      (refill_done ? refill_paddr[11:6] : rockettile_icache_tag_array_tag_rdata_addr),
    .RW0_en    (rockettile_icache_tag_array_tag_rdata_en | refill_done),
    .RW0_clk   (clock),
    .RW0_wmode (refill_one_beat),
    .RW0_wdata ({refillError, refill_paddr[31:12]}),
    .RW0_rdata (_rockettile_icache_tag_array_ext_RW0_rdata)
  );
  rockettile_icache_data_arrays_512x32 rockettile_icache_data_arrays_0_ext (
    .RW0_addr  (refill_one_beat ? _mem_idx_T_6 | refill_cnt : io_req_bits_addr[11:3]),
    .RW0_en    (rockettile_icache_data_arrays_0_dout_en | wen),
    .RW0_clk   (clock),
    .RW0_wmode (refill_one_beat),
    .RW0_wdata (auto_master_out_d_bits_data[31:0]),
    .RW0_rdata (_rockettile_icache_data_arrays_0_ext_RW0_rdata)
  );
  rockettile_icache_data_arrays_512x32 rockettile_icache_data_arrays_1_ext (
    .RW0_addr  (refill_one_beat ? _mem_idx_T_6 | refill_cnt : io_req_bits_addr[11:3]),
    .RW0_en    (rockettile_icache_data_arrays_1_dout_1_en | wen_1),
    .RW0_clk   (clock),
    .RW0_wmode (refill_one_beat),
    .RW0_wdata (auto_master_out_d_bits_data[63:32]),
    .RW0_rdata (_rockettile_icache_data_arrays_1_ext_RW0_rdata)
  );
  assign auto_master_out_a_valid = s2_request_refill;
  assign auto_master_out_a_bits_address = {refill_paddr[31:6], 6'h0};
  assign auto_master_out_a_bits_user_amba_prot_readalloc = io_s2_cacheable;
  assign auto_master_out_a_bits_user_amba_prot_writealloc = io_s2_cacheable;
  assign io_resp_valid = s2_valid & s2_hit;
  assign io_resp_bits_data = s2_dout_0;
  assign io_resp_bits_ae = s2_tl_error;
endmodule