onur
49 lines
1.4 KiB
Systemverilog
49 lines
1.4 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module Queue1_TLBundleA_a14d64s2k1z4u(
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input clock,
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reset,
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output io_enq_ready,
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input io_enq_valid,
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input [2:0] io_enq_bits_opcode,
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io_enq_bits_param,
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input [3:0] io_enq_bits_size,
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input [1:0] io_enq_bits_source,
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input [13:0] io_enq_bits_address,
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input [7:0] io_enq_bits_mask,
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input [63:0] io_enq_bits_data,
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input io_enq_bits_corrupt,
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io_deq_ready,
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output io_deq_valid,
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output [2:0] io_deq_bits_opcode,
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output [3:0] io_deq_bits_size,
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output [1:0] io_deq_bits_source
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);
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reg [98:0] ram;
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reg maybe_full;
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always @(posedge clock) begin
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automatic logic do_enq;
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do_enq = ~maybe_full & io_enq_valid;
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if (reset)
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maybe_full <= 1'h0;
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else if (do_enq != (io_deq_ready & maybe_full))
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maybe_full <= do_enq;
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if (do_enq)
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ram <=
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{io_enq_bits_opcode,
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io_enq_bits_param,
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io_enq_bits_size,
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io_enq_bits_source,
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io_enq_bits_address,
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io_enq_bits_mask,
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io_enq_bits_data,
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io_enq_bits_corrupt};
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end // always @(posedge)
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assign io_enq_ready = ~maybe_full;
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assign io_deq_valid = maybe_full;
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assign io_deq_bits_opcode = ram[98:96];
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assign io_deq_bits_size = ram[92:89];
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assign io_deq_bits_source = ram[88:87];
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endmodule
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