onur
58 lines
2.0 KiB
Systemverilog
58 lines
2.0 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module Queue1_TLBundleD_a29d32s7k1z2u(
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input clock,
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reset,
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output io_enq_ready,
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input io_enq_valid,
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input [2:0] io_enq_bits_opcode,
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input [1:0] io_enq_bits_size,
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input [6:0] io_enq_bits_source,
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input io_enq_bits_denied,
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input [31:0] io_enq_bits_data,
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input io_enq_bits_corrupt,
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io_deq_ready,
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output io_deq_valid,
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output [2:0] io_deq_bits_opcode,
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output [1:0] io_deq_bits_param,
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io_deq_bits_size,
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output [6:0] io_deq_bits_source,
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output io_deq_bits_sink,
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io_deq_bits_denied,
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output [31:0] io_deq_bits_data,
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output io_deq_bits_corrupt
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);
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reg [48:0] ram;
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reg maybe_full;
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wire io_deq_valid_0 = io_enq_valid | maybe_full;
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always @(posedge clock) begin
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automatic logic do_enq;
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do_enq = ~(~maybe_full & io_deq_ready) & ~maybe_full & io_enq_valid;
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if (reset)
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maybe_full <= 1'h0;
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else if (do_enq != (maybe_full & io_deq_ready & io_deq_valid_0))
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maybe_full <= do_enq;
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if (do_enq)
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ram <=
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{io_enq_bits_opcode,
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2'h0,
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io_enq_bits_size,
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io_enq_bits_source,
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1'h0,
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io_enq_bits_denied,
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io_enq_bits_data,
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io_enq_bits_corrupt};
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end // always @(posedge)
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assign io_enq_ready = ~maybe_full;
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assign io_deq_valid = io_deq_valid_0;
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assign io_deq_bits_opcode = maybe_full ? ram[48:46] : io_enq_bits_opcode;
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assign io_deq_bits_param = maybe_full ? ram[45:44] : 2'h0;
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assign io_deq_bits_size = maybe_full ? ram[43:42] : io_enq_bits_size;
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assign io_deq_bits_source = maybe_full ? ram[41:35] : io_enq_bits_source;
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assign io_deq_bits_sink = maybe_full & ram[34];
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assign io_deq_bits_denied = maybe_full ? ram[33] : io_enq_bits_denied;
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assign io_deq_bits_data = maybe_full ? ram[32:1] : io_enq_bits_data;
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assign io_deq_bits_corrupt = maybe_full ? ram[0] : io_enq_bits_corrupt;
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endmodule
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