onur
78 lines
2.3 KiB
Systemverilog
78 lines
2.3 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module Queue2_TLBundleA_a32d64s2k1z3u(
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input clock,
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reset,
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output io_enq_ready,
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input io_enq_valid,
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input [2:0] io_enq_bits_opcode,
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io_enq_bits_param,
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io_enq_bits_size,
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input [1:0] io_enq_bits_source,
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input [31:0] io_enq_bits_address,
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input [7:0] io_enq_bits_mask,
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input [63:0] io_enq_bits_data,
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input io_enq_bits_corrupt,
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io_deq_ready,
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output io_deq_valid,
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output [2:0] io_deq_bits_opcode,
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io_deq_bits_param,
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io_deq_bits_size,
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output [1:0] io_deq_bits_source,
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output [31:0] io_deq_bits_address,
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output [7:0] io_deq_bits_mask,
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output [63:0] io_deq_bits_data
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);
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wire [114:0] _ram_ext_R0_data;
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reg enq_ptr_value;
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reg deq_ptr_value;
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reg maybe_full;
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wire ptr_match = enq_ptr_value == deq_ptr_value;
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wire empty = ptr_match & ~maybe_full;
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wire full = ptr_match & maybe_full;
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wire do_enq = ~full & io_enq_valid;
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always @(posedge clock) begin
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if (reset) begin
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enq_ptr_value <= 1'h0;
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deq_ptr_value <= 1'h0;
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maybe_full <= 1'h0;
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end
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else begin
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automatic logic do_deq = io_deq_ready & ~empty;
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if (do_enq)
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enq_ptr_value <= enq_ptr_value - 1'h1;
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if (do_deq)
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deq_ptr_value <= deq_ptr_value - 1'h1;
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if (do_enq != do_deq)
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maybe_full <= do_enq;
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end
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end // always @(posedge)
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ram_2x115 ram_ext (
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.R0_addr (deq_ptr_value),
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.R0_en (1'h1),
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.R0_clk (clock),
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.R0_data (_ram_ext_R0_data),
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.W0_addr (enq_ptr_value),
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.W0_en (do_enq),
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.W0_clk (clock),
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.W0_data
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({io_enq_bits_opcode,
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io_enq_bits_param,
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io_enq_bits_size,
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io_enq_bits_source,
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io_enq_bits_address,
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io_enq_bits_mask,
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io_enq_bits_data})
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);
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assign io_enq_ready = ~full;
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assign io_deq_valid = ~empty;
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assign io_deq_bits_opcode = _ram_ext_R0_data[114:112];
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assign io_deq_bits_param = _ram_ext_R0_data[111:109];
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assign io_deq_bits_size = _ram_ext_R0_data[108:106];
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assign io_deq_bits_source = _ram_ext_R0_data[105:104];
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assign io_deq_bits_address = _ram_ext_R0_data[103:72];
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assign io_deq_bits_mask = _ram_ext_R0_data[71:64];
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assign io_deq_bits_data = _ram_ext_R0_data[63:0];
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endmodule
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