onur
18 lines
391 B
Systemverilog
18 lines
391 B
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module ResetCatchAndSync_d3(
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input clock,
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reset,
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output io_sync_reset
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);
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wire _io_sync_reset_chain_io_q;
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AsyncResetSynchronizerShiftReg_w1_d3_i0 io_sync_reset_chain (
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.clock (clock),
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.reset (reset),
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.io_d (1'h1),
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.io_q (_io_sync_reset_chain_io_q)
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);
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assign io_sync_reset = ~_io_sync_reset_chain_io_q;
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endmodule
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