onur
77 lines
3.2 KiB
Systemverilog
77 lines
3.2 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
|
|
module RocketALU(
|
|
input io_dw,
|
|
input [4:0] io_fn,
|
|
input [63:0] io_in2,
|
|
io_in1,
|
|
output [63:0] io_out,
|
|
io_adder_out,
|
|
output io_cmp_out
|
|
);
|
|
|
|
wire [63:0] in2_inv = {64{io_fn[3]}} ^ io_in2;
|
|
wire [63:0] in1_xor_in2 = io_in1 ^ in2_inv;
|
|
wire [63:0] _io_adder_out_T_3 = io_in1 + in2_inv + {63'h0, io_fn[3]};
|
|
wire slt =
|
|
io_in1[63] == io_in2[63] ? _io_adder_out_T_3[63] : io_fn[1] ? io_in2[63] : io_in1[63];
|
|
wire [31:0] shin_hi = io_dw ? io_in1[63:32] : {32{io_fn[3] & io_in1[31]}};
|
|
wire _shout_T = io_fn == 5'h5;
|
|
wire _shout_T_1 = io_fn == 5'hB;
|
|
wire _bext_mask_T = io_fn == 5'h13;
|
|
wire [63:0] _shin_T_16 = {32'h0, shin_hi} | {io_in1[31:0], 32'h0};
|
|
wire [63:0] _shin_T_26 =
|
|
{16'h0, _shin_T_16[63:16] & 48'hFFFF0000FFFF}
|
|
| {_shin_T_16[47:0] & 48'hFFFF0000FFFF, 16'h0};
|
|
wire [63:0] _shin_T_36 =
|
|
{8'h0, _shin_T_26[63:8] & 56'hFF00FF00FF00FF}
|
|
| {_shin_T_26[55:0] & 56'hFF00FF00FF00FF, 8'h0};
|
|
wire [63:0] _shin_T_46 =
|
|
{4'h0, _shin_T_36[63:4] & 60'hF0F0F0F0F0F0F0F}
|
|
| {_shin_T_36[59:0] & 60'hF0F0F0F0F0F0F0F, 4'h0};
|
|
wire [63:0] _shin_T_56 =
|
|
{2'h0, _shin_T_46[63:2] & 62'h3333333333333333}
|
|
| {_shin_T_46[61:0] & 62'h3333333333333333, 2'h0};
|
|
wire [63:0] shin =
|
|
_shout_T | _shout_T_1 | io_fn == 5'h12 | _bext_mask_T
|
|
? {shin_hi, io_in1[31:0]}
|
|
: {1'h0, _shin_T_56[63:1] & 63'h5555555555555555}
|
|
| {_shin_T_56[62:0] & 63'h5555555555555555, 1'h0};
|
|
wire [64:0] _shout_r_T_5 =
|
|
$unsigned($signed($signed({io_fn[3] & shin[63], shin})
|
|
>>> {59'h0, io_in2[5] & io_dw, io_in2[4:0]}));
|
|
wire [63:0] _shout_l_T_8 = {32'h0, _shout_r_T_5[63:32]} | {_shout_r_T_5[31:0], 32'h0};
|
|
wire [63:0] _shout_l_T_18 =
|
|
{16'h0, _shout_l_T_8[63:16] & 48'hFFFF0000FFFF}
|
|
| {_shout_l_T_8[47:0] & 48'hFFFF0000FFFF, 16'h0};
|
|
wire [63:0] _shout_l_T_28 =
|
|
{8'h0, _shout_l_T_18[63:8] & 56'hFF00FF00FF00FF}
|
|
| {_shout_l_T_18[55:0] & 56'hFF00FF00FF00FF, 8'h0};
|
|
wire [63:0] _shout_l_T_38 =
|
|
{4'h0, _shout_l_T_28[63:4] & 60'hF0F0F0F0F0F0F0F}
|
|
| {_shout_l_T_28[59:0] & 60'hF0F0F0F0F0F0F0F, 4'h0};
|
|
wire [63:0] _shout_l_T_48 =
|
|
{2'h0, _shout_l_T_38[63:2] & 62'h3333333333333333}
|
|
| {_shout_l_T_38[61:0] & 62'h3333333333333333, 2'h0};
|
|
wire _logic_T_8 = io_fn == 5'h6;
|
|
wire _logic_T_11 = io_fn == 5'h19;
|
|
wire [63:0] out =
|
|
io_fn == 5'hA | io_fn == 5'h0
|
|
? _io_adder_out_T_3
|
|
: {63'h0, io_fn > 5'hB & ~(io_fn[4]) & slt}
|
|
| (io_fn == 5'h4 | _logic_T_8 | _logic_T_11 | io_fn == 5'h1A
|
|
? in1_xor_in2
|
|
: 64'h0)
|
|
| (_logic_T_8 | io_fn == 5'h7 | _logic_T_11 | io_fn == 5'h18
|
|
? io_in1 & in2_inv
|
|
: 64'h0)
|
|
| (_shout_T | _shout_T_1 | _bext_mask_T ? _shout_r_T_5[63:0] : 64'h0)
|
|
| (io_fn == 5'h1
|
|
? {1'h0, _shout_l_T_48[63:1] & 63'h5555555555555555}
|
|
| {_shout_l_T_48[62:0] & 63'h5555555555555555, 1'h0}
|
|
: 64'h0);
|
|
assign io_out = io_dw ? out : {{32{out[31]}}, out[31:0]};
|
|
assign io_adder_out = _io_adder_out_T_3;
|
|
assign io_cmp_out = io_fn[0] ^ (io_fn[3] ? slt : in1_xor_in2 == 64'h0);
|
|
endmodule
|
|
|