onur
115 lines
5.6 KiB
Systemverilog
115 lines
5.6 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module RoundAnyRawFNToRecFN_4(
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input io_invalidExc,
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io_infiniteExc,
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io_in_isNaN,
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io_in_isInf,
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io_in_isZero,
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io_in_sign,
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input [12:0] io_in_sExp,
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input [55:0] io_in_sig,
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input [2:0] io_roundingMode,
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output [64:0] io_out,
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output [4:0] io_exceptionFlags
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);
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wire roundingMode_near_even = io_roundingMode == 3'h0;
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wire roundingMode_odd = io_roundingMode == 3'h6;
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wire roundMagUp =
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io_roundingMode == 3'h2 & io_in_sign | io_roundingMode == 3'h3 & ~io_in_sign;
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wire [11:0] _roundMask_T_1 = ~(io_in_sExp[11:0]);
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wire [64:0] roundMask_shift =
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$unsigned($signed(65'sh10000000000000000 >>> _roundMask_T_1[5:0]));
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wire [31:0] _roundMask_T_12 =
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{16'h0, roundMask_shift[44:29]} | {roundMask_shift[28:13], 16'h0};
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wire [31:0] _roundMask_T_22 =
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{8'h0, _roundMask_T_12[31:8] & 24'hFF00FF}
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| {_roundMask_T_12[23:0] & 24'hFF00FF, 8'h0};
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wire [31:0] _roundMask_T_32 =
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{4'h0, _roundMask_T_22[31:4] & 28'hF0F0F0F}
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| {_roundMask_T_22[27:0] & 28'hF0F0F0F, 4'h0};
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wire [31:0] _roundMask_T_42 =
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{2'h0, _roundMask_T_32[31:2] & 30'h33333333}
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| {_roundMask_T_32[29:0] & 30'h33333333, 2'h0};
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wire [15:0] _roundMask_T_63 =
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{8'h0, roundMask_shift[60:53]} | {roundMask_shift[52:45], 8'h0};
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wire [15:0] _roundMask_T_73 =
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{4'h0, _roundMask_T_63[15:4] & 12'hF0F} | {_roundMask_T_63[11:0] & 12'hF0F, 4'h0};
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wire [15:0] _roundMask_T_83 =
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{2'h0, _roundMask_T_73[15:2] & 14'h3333} | {_roundMask_T_73[13:0] & 14'h3333, 2'h0};
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wire [64:0] roundMask_shift_1 =
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$unsigned($signed(65'sh10000000000000000 >>> _roundMask_T_1[5:0]));
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wire [53:0] _roundMask_T_128 =
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_roundMask_T_1[11]
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? (_roundMask_T_1[10]
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? {~(_roundMask_T_1[9] | _roundMask_T_1[8] | _roundMask_T_1[7]
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| _roundMask_T_1[6]
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? 51'h0
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: ~{{1'h0, _roundMask_T_42[31:1] & 31'h55555555}
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| {_roundMask_T_42[30:0] & 31'h55555555, 1'h0},
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{1'h0, _roundMask_T_83[15:1] & 15'h5555}
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| {_roundMask_T_83[14:0] & 15'h5555, 1'h0},
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roundMask_shift[61],
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roundMask_shift[62],
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roundMask_shift[63]}),
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3'h7}
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: {51'h0,
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_roundMask_T_1[9] & _roundMask_T_1[8] & _roundMask_T_1[7]
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& _roundMask_T_1[6]
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? {roundMask_shift_1[0], roundMask_shift_1[1], roundMask_shift_1[2]}
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: 3'h0})
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: 54'h0;
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wire _common_underflow_T_4 = _roundMask_T_128[0] | io_in_sig[55];
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wire [54:0] _GEN = {1'h1, ~(_roundMask_T_128[53:1]), ~_common_underflow_T_4};
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wire [54:0] _GEN_0 = {_roundMask_T_128[53:1], _common_underflow_T_4, 1'h1};
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wire [54:0] _roundPosBit_T = io_in_sig[55:1] & _GEN & _GEN_0;
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wire roundPosBit = |_roundPosBit_T;
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wire [54:0] _anyRoundExtra_T = io_in_sig[54:0] & _GEN_0;
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wire anyRound = |{_roundPosBit_T, _anyRoundExtra_T};
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wire _overflow_roundMagUp_T = roundingMode_near_even | io_roundingMode == 3'h4;
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wire [54:0] roundedSig =
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_overflow_roundMagUp_T & roundPosBit | roundMagUp & anyRound
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? {1'h0, io_in_sig[55:2] | {_roundMask_T_128[53:1], _common_underflow_T_4}} + 55'h1
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& ~(roundingMode_near_even & roundPosBit & _anyRoundExtra_T == 55'h0
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? {_roundMask_T_128[53:1], _common_underflow_T_4, 1'h1}
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: 55'h0)
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: {1'h0, io_in_sig[55:2] & {~(_roundMask_T_128[53:1]), ~_common_underflow_T_4}}
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| (roundingMode_odd & anyRound ? _GEN & _GEN_0 : 55'h0);
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wire [13:0] sRoundedExp = {io_in_sExp[12], io_in_sExp} + {12'h0, roundedSig[54:53]};
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wire common_totalUnderflow = $signed(sRoundedExp) < 14'sh3CE;
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wire isNaNOut = io_invalidExc | io_in_isNaN;
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wire notNaN_isSpecialInfOut = io_infiniteExc | io_in_isInf;
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wire commonCase = ~isNaNOut & ~notNaN_isSpecialInfOut & ~io_in_isZero;
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wire overflow = commonCase & $signed(sRoundedExp[13:10]) > 4'sh2;
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wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp;
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wire pegMinNonzeroMagOut =
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commonCase & common_totalUnderflow & (roundMagUp | roundingMode_odd);
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wire pegMaxFiniteMagOut = overflow & ~overflow_roundMagUp;
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wire notNaN_isInfOut = notNaN_isSpecialInfOut | overflow & overflow_roundMagUp;
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assign io_out =
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{~isNaNOut & io_in_sign,
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sRoundedExp[11:0] & ~(io_in_isZero | common_totalUnderflow ? 12'hE00 : 12'h0)
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& ~(pegMinNonzeroMagOut ? 12'hC31 : 12'h0) & {1'h1, ~pegMaxFiniteMagOut, 10'h3FF}
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& {2'h3, ~notNaN_isInfOut, 9'h1FF} | (pegMinNonzeroMagOut ? 12'h3CE : 12'h0)
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| (pegMaxFiniteMagOut ? 12'hBFF : 12'h0) | (notNaN_isInfOut ? 12'hC00 : 12'h0)
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| (isNaNOut ? 12'hE00 : 12'h0),
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(isNaNOut | io_in_isZero | common_totalUnderflow
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? {isNaNOut, 51'h0}
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: io_in_sig[55] ? roundedSig[52:1] : roundedSig[51:0])
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| {52{pegMaxFiniteMagOut}}};
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assign io_exceptionFlags =
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{io_invalidExc,
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io_infiniteExc,
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overflow,
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commonCase
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& (common_totalUnderflow | anyRound & io_in_sExp[12:11] != 2'h1
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& (io_in_sig[55] ? _roundMask_T_128[1] : _common_underflow_T_4)
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& ~(~(io_in_sig[55] ? _roundMask_T_128[2] : _roundMask_T_128[1])
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& (io_in_sig[55] ? roundedSig[54] : roundedSig[53]) & roundPosBit
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& (_overflow_roundMagUp_T & (io_in_sig[55] ? io_in_sig[2] : io_in_sig[1])
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| roundMagUp & (|{io_in_sig[55] & io_in_sig[2], io_in_sig[1:0]})))),
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overflow | commonCase
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& (|{common_totalUnderflow, _roundPosBit_T, _anyRoundExtra_T})};
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endmodule
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