onur
132 lines
5.0 KiB
Systemverilog
132 lines
5.0 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module ShiftQueue(
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input clock,
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reset,
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output io_enq_ready,
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input io_enq_valid,
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input [33:0] io_enq_bits_pc,
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input [31:0] io_enq_bits_data,
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input io_enq_bits_xcpt_pf_inst,
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io_enq_bits_xcpt_ae_inst,
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io_enq_bits_replay,
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io_deq_ready,
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output io_deq_valid,
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output [33:0] io_deq_bits_pc,
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output [31:0] io_deq_bits_data,
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output io_deq_bits_xcpt_pf_inst,
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io_deq_bits_xcpt_ae_inst,
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io_deq_bits_replay,
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output [4:0] io_mask
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);
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reg valid_0;
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reg valid_1;
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reg valid_2;
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reg valid_3;
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reg valid_4;
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reg [33:0] elts_0_pc;
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reg [31:0] elts_0_data;
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reg elts_0_xcpt_pf_inst;
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reg elts_0_xcpt_ae_inst;
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reg elts_0_replay;
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reg [33:0] elts_1_pc;
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reg [31:0] elts_1_data;
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reg elts_1_xcpt_pf_inst;
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reg elts_1_xcpt_ae_inst;
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reg elts_1_replay;
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reg [33:0] elts_2_pc;
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reg [31:0] elts_2_data;
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reg elts_2_xcpt_pf_inst;
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reg elts_2_xcpt_ae_inst;
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reg elts_2_replay;
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reg [33:0] elts_3_pc;
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reg [31:0] elts_3_data;
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reg elts_3_xcpt_pf_inst;
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reg elts_3_xcpt_ae_inst;
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reg elts_3_replay;
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reg [33:0] elts_4_pc;
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reg [31:0] elts_4_data;
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reg elts_4_xcpt_pf_inst;
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reg elts_4_xcpt_ae_inst;
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reg elts_4_replay;
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always @(posedge clock) begin
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automatic logic _valid_4_T_4;
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_valid_4_T_4 = ~valid_4 & io_enq_valid;
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if (reset) begin
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valid_0 <= 1'h0;
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valid_1 <= 1'h0;
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valid_2 <= 1'h0;
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valid_3 <= 1'h0;
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valid_4 <= 1'h0;
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end
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else begin
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valid_0 <= io_deq_ready ? valid_1 | _valid_4_T_4 & valid_0 : _valid_4_T_4 | valid_0;
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valid_1 <=
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io_deq_ready
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? valid_2 | _valid_4_T_4 & valid_1
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: _valid_4_T_4 & valid_0 | valid_1;
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valid_2 <=
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io_deq_ready
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? valid_3 | _valid_4_T_4 & valid_2
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: _valid_4_T_4 & valid_1 | valid_2;
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valid_3 <=
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io_deq_ready
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? valid_4 | _valid_4_T_4 & valid_3
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: _valid_4_T_4 & valid_2 | valid_3;
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valid_4 <= io_deq_ready ? _valid_4_T_4 & valid_4 : _valid_4_T_4 & valid_3 | valid_4;
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end
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if (io_deq_ready ? valid_1 | _valid_4_T_4 & valid_0 : _valid_4_T_4 & ~valid_0) begin
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elts_0_pc <= valid_1 ? elts_1_pc : io_enq_bits_pc;
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elts_0_data <= valid_1 ? elts_1_data : io_enq_bits_data;
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elts_0_xcpt_pf_inst <= valid_1 ? elts_1_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst;
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elts_0_xcpt_ae_inst <= valid_1 ? elts_1_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst;
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elts_0_replay <= valid_1 ? elts_1_replay : io_enq_bits_replay;
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end
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if (io_deq_ready
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? valid_2 | _valid_4_T_4 & valid_1
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: _valid_4_T_4 & valid_0 & ~valid_1) begin
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elts_1_pc <= valid_2 ? elts_2_pc : io_enq_bits_pc;
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elts_1_data <= valid_2 ? elts_2_data : io_enq_bits_data;
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elts_1_xcpt_pf_inst <= valid_2 ? elts_2_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst;
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elts_1_xcpt_ae_inst <= valid_2 ? elts_2_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst;
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elts_1_replay <= valid_2 ? elts_2_replay : io_enq_bits_replay;
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end
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if (io_deq_ready
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? valid_3 | _valid_4_T_4 & valid_2
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: _valid_4_T_4 & valid_1 & ~valid_2) begin
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elts_2_pc <= valid_3 ? elts_3_pc : io_enq_bits_pc;
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elts_2_data <= valid_3 ? elts_3_data : io_enq_bits_data;
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elts_2_xcpt_pf_inst <= valid_3 ? elts_3_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst;
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elts_2_xcpt_ae_inst <= valid_3 ? elts_3_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst;
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elts_2_replay <= valid_3 ? elts_3_replay : io_enq_bits_replay;
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end
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if (io_deq_ready
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? valid_4 | _valid_4_T_4 & valid_3
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: _valid_4_T_4 & valid_2 & ~valid_3) begin
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elts_3_pc <= valid_4 ? elts_4_pc : io_enq_bits_pc;
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elts_3_data <= valid_4 ? elts_4_data : io_enq_bits_data;
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elts_3_xcpt_pf_inst <= valid_4 ? elts_4_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst;
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elts_3_xcpt_ae_inst <= valid_4 ? elts_4_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst;
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elts_3_replay <= valid_4 ? elts_4_replay : io_enq_bits_replay;
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end
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if (io_deq_ready ? _valid_4_T_4 & valid_4 : _valid_4_T_4 & valid_3) begin
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elts_4_pc <= io_enq_bits_pc;
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elts_4_data <= io_enq_bits_data;
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elts_4_xcpt_pf_inst <= io_enq_bits_xcpt_pf_inst;
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elts_4_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst;
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elts_4_replay <= io_enq_bits_replay;
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end
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end // always @(posedge)
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assign io_enq_ready = ~valid_4;
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assign io_deq_valid = io_enq_valid | valid_0;
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assign io_deq_bits_pc = valid_0 ? elts_0_pc : io_enq_bits_pc;
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assign io_deq_bits_data = valid_0 ? elts_0_data : io_enq_bits_data;
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assign io_deq_bits_xcpt_pf_inst =
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valid_0 ? elts_0_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst;
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assign io_deq_bits_xcpt_ae_inst =
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valid_0 ? elts_0_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst;
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assign io_deq_bits_replay = valid_0 ? elts_0_replay : io_enq_bits_replay;
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assign io_mask = {valid_4, valid_3, valid_2, valid_1, valid_0};
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endmodule
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