87 lines
3.3 KiB
Systemverilog
87 lines
3.3 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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// Users can define 'PRINTF_COND' to add an extra gate to prints.
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`ifndef PRINTF_COND_
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`ifdef PRINTF_COND
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`define PRINTF_COND_ (`PRINTF_COND)
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`else // PRINTF_COND
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`define PRINTF_COND_ 1
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`endif // PRINTF_COND
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`endif // not def PRINTF_COND_
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module TLError(
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input clock,
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reset,
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output auto_in_a_ready,
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input auto_in_a_valid,
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input [2:0] auto_in_a_bits_opcode,
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auto_in_a_bits_param,
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input [3:0] auto_in_a_bits_size,
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input [1:0] auto_in_a_bits_source,
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input [13:0] auto_in_a_bits_address,
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input [7:0] auto_in_a_bits_mask,
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input [63:0] auto_in_a_bits_data,
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input auto_in_a_bits_corrupt,
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auto_in_d_ready,
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output auto_in_d_valid,
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output [2:0] auto_in_d_bits_opcode,
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output [3:0] auto_in_d_bits_size,
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output [1:0] auto_in_d_bits_source,
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output auto_in_d_bits_corrupt
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);
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wire [2:0] da_bits_opcode;
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wire _a_q_io_deq_valid;
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wire [2:0] _a_q_io_deq_bits_opcode;
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wire [3:0] _a_q_io_deq_bits_size;
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wire [7:0][2:0] _GEN = '{3'h4, 3'h4, 3'h2, 3'h1, 3'h1, 3'h1, 3'h0, 3'h0};
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wire [26:0] _GEN_0 = {23'h0, _a_q_io_deq_bits_size};
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wire [26:0] _a_last_beats1_decode_T = 27'hFFF << _GEN_0;
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wire [8:0] a_last_beats1 =
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_a_q_io_deq_bits_opcode[2] ? 9'h0 : ~(_a_last_beats1_decode_T[11:3]);
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reg [8:0] a_last_counter;
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wire a_last = a_last_counter == 9'h1 | a_last_beats1 == 9'h0;
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wire [26:0] _r_beats1_decode_T = 27'hFFF << _GEN_0;
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wire [8:0] r_beats1 = da_bits_opcode[0] ? ~(_r_beats1_decode_T[11:3]) : 9'h0;
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reg [8:0] r_counter;
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wire a_q_io_deq_ready =
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auto_in_d_ready & (r_counter == 9'h1 | r_beats1 == 9'h0) | ~a_last;
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wire da_valid = _a_q_io_deq_valid & a_last;
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assign da_bits_opcode = _GEN[_a_q_io_deq_bits_opcode];
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always @(posedge clock) begin
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if (reset) begin
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a_last_counter <= 9'h0;
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r_counter <= 9'h0;
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end
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else begin
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if (a_q_io_deq_ready & _a_q_io_deq_valid)
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a_last_counter <= a_last_counter == 9'h0 ? a_last_beats1 : a_last_counter - 9'h1;
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if (auto_in_d_ready & da_valid)
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r_counter <= r_counter == 9'h0 ? r_beats1 : r_counter - 9'h1;
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end
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end // always @(posedge)
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Queue1_TLBundleA_a14d64s2k1z4u a_q (
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.clock (clock),
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.reset (reset),
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.io_enq_ready (auto_in_a_ready),
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.io_enq_valid (auto_in_a_valid),
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.io_enq_bits_opcode (auto_in_a_bits_opcode),
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.io_enq_bits_param (auto_in_a_bits_param),
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.io_enq_bits_size (auto_in_a_bits_size),
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.io_enq_bits_source (auto_in_a_bits_source),
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.io_enq_bits_address (auto_in_a_bits_address),
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.io_enq_bits_mask (auto_in_a_bits_mask),
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.io_enq_bits_data (auto_in_a_bits_data),
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.io_enq_bits_corrupt (auto_in_a_bits_corrupt),
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.io_deq_ready (a_q_io_deq_ready),
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.io_deq_valid (_a_q_io_deq_valid),
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.io_deq_bits_opcode (_a_q_io_deq_bits_opcode),
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.io_deq_bits_size (_a_q_io_deq_bits_size),
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.io_deq_bits_source (auto_in_d_bits_source)
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);
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assign auto_in_d_valid = da_valid;
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assign auto_in_d_bits_opcode = da_bits_opcode;
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assign auto_in_d_bits_size = _a_q_io_deq_bits_size;
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assign auto_in_d_bits_corrupt = da_bits_opcode[0];
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endmodule
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