onur
184 lines
7.1 KiB
Systemverilog
184 lines
7.1 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module TLFpgaUART(
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input clock,
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reset,
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output auto_in_a_ready,
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input auto_in_a_valid,
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input [2:0] auto_in_a_bits_opcode,
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input [1:0] auto_in_a_bits_size,
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input [5:0] auto_in_a_bits_source,
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input [28:0] auto_in_a_bits_address,
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input [7:0] auto_in_a_bits_mask,
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input [63:0] auto_in_a_bits_data,
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input auto_in_d_ready,
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output auto_in_d_valid,
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output [2:0] auto_in_d_bits_opcode,
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output [1:0] auto_in_d_bits_size,
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output [5:0] auto_in_d_bits_source,
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output [63:0] auto_in_d_bits_data,
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output auto_txd_out,
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input auto_rxd_in
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);
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wire _out_back_front_q_io_deq_valid;
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wire _out_back_front_q_io_deq_bits_read;
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wire [8:0] _out_back_front_q_io_deq_bits_index;
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wire [63:0] _out_back_front_q_io_deq_bits_data;
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wire [7:0] _out_back_front_q_io_deq_bits_mask;
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reg [31:0] clockFrequency;
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reg [31:0] baudRate;
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reg [31:0] divisor;
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reg [9:0] txReg;
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reg txBusy;
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reg [31:0] txDiv;
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reg [3:0] txCount;
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reg rxSync_REG;
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reg rxSync;
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reg rxPrev;
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reg rxBusy;
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reg [31:0] rxDiv;
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reg [3:0] rxCount;
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reg [7:0] rxShift;
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reg [7:0] rxData;
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reg rxValid;
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wire _out_out_bits_data_T_1 =
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_out_back_front_q_io_deq_bits_index[8:2] == 7'h0;
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wire [3:0] _out_backSel_T = 4'h1 << _out_back_front_q_io_deq_bits_index[1:0];
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wire _out_wofireMux_T = _out_back_front_q_io_deq_valid & auto_in_d_ready;
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wire _out_wofireMux_T_2 =
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_out_wofireMux_T & ~_out_back_front_q_io_deq_bits_read;
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wire out_woready_5 =
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_out_wofireMux_T_2 & _out_backSel_T[2] & _out_out_bits_data_T_1;
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wire [3:0][63:0] _GEN =
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{{{32'h0, divisor}},
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{{baudRate, clockFrequency}},
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{{31'h0, rxValid, 31'h0, ~txBusy}},
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{{24'h0, rxData, 32'h0}}};
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always @(posedge clock) begin
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if (reset) begin
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clockFrequency <= 32'h5F5E100;
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baudRate <= 32'h1C200;
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divisor <= 32'h364;
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txReg <= 10'h1;
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txBusy <= 1'h0;
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txDiv <= 32'h0;
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txCount <= 4'h0;
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rxSync_REG <= 1'h1;
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rxSync <= 1'h1;
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rxPrev <= 1'h1;
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rxBusy <= 1'h0;
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rxDiv <= 32'h0;
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rxCount <= 4'h0;
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rxShift <= 8'h0;
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rxData <= 8'h0;
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rxValid <= 1'h0;
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end
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else begin
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automatic logic _rxStartDelay_T;
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automatic logic [31:0] divisorMinusOne;
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automatic logic _GEN_0;
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automatic logic _GEN_1;
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automatic logic _GEN_2 = ~rxBusy & rxPrev & ~rxSync;
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automatic logic _GEN_3;
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automatic logic _GEN_4;
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automatic logic _GEN_5;
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automatic logic _out_T_10 =
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_out_wofireMux_T_2 & _out_backSel_T[0] & _out_out_bits_data_T_1
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& _out_back_front_q_io_deq_bits_mask[0] & ~txBusy;
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automatic logic [31:0] _out_womask_T_6 =
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{{8{_out_back_front_q_io_deq_bits_mask[3]}},
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{8{_out_back_front_q_io_deq_bits_mask[2]}},
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{8{_out_back_front_q_io_deq_bits_mask[1]}},
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{8{_out_back_front_q_io_deq_bits_mask[0]}}};
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_rxStartDelay_T = divisor < 32'h2;
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divisorMinusOne = _rxStartDelay_T ? 32'h1 : divisor - 32'h1;
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_GEN_0 = txDiv == divisorMinusOne;
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_GEN_1 = txCount == 4'h0;
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_GEN_3 = rxDiv == 32'h0;
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_GEN_4 = rxBusy & _GEN_3 & ~(rxCount[3]);
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_GEN_5 = rxBusy & _GEN_3;
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if (out_woready_5 & (&_out_womask_T_6))
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clockFrequency <= _out_back_front_q_io_deq_bits_data[31:0];
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if (out_woready_5
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& (&{{8{_out_back_front_q_io_deq_bits_mask[7]}},
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{8{_out_back_front_q_io_deq_bits_mask[6]}},
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{8{_out_back_front_q_io_deq_bits_mask[5]}},
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{8{_out_back_front_q_io_deq_bits_mask[4]}}}))
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baudRate <= _out_back_front_q_io_deq_bits_data[63:32];
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if (_out_wofireMux_T_2 & _out_backSel_T[3] & _out_out_bits_data_T_1
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& (&_out_womask_T_6))
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divisor <= _out_back_front_q_io_deq_bits_data[31:0];
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if (_out_T_10) begin
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txReg <= {1'h1, _out_back_front_q_io_deq_bits_data[7:0], 1'h0};
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txDiv <= 32'h0;
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txCount <= 4'h9;
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end
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else begin
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automatic logic _GEN_6;
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_GEN_6 = txBusy & _GEN_0;
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if (_GEN_6)
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txReg <= _GEN_1 ? 10'h3FF : {1'h1, txReg[9:1]};
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if (txBusy)
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txDiv <= _GEN_0 ? 32'h0 : txDiv + 32'h1;
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if (~_GEN_6 | _GEN_1) begin
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end
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else
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txCount <= txCount - 4'h1;
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end
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txBusy <= _out_T_10 | ~(txBusy & _GEN_0 & _GEN_1) & txBusy;
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rxSync_REG <= auto_rxd_in;
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rxSync <= rxSync_REG;
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rxPrev <= rxSync;
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rxBusy <= _GEN_2 | (~_GEN_5 | ~(rxCount[3])) & rxBusy;
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if (_GEN_2) begin
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rxDiv <= _rxStartDelay_T ? 32'h1 : divisor + {1'h0, divisor[31:1]} - 32'h1;
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rxCount <= 4'h0;
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end
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else begin
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if (rxBusy)
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rxDiv <= _GEN_3 ? divisorMinusOne : rxDiv - 32'h1;
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if (_GEN_4)
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rxCount <= rxCount + 4'h1;
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end
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if (_GEN_2 | ~_GEN_4) begin
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end
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else
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rxShift <= {rxSync, rxShift[7:1]};
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if (_GEN_2 | ~(_GEN_5 & rxCount[3] & rxSync)) begin
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end
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else
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rxData <= rxShift;
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rxValid <=
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~(_out_wofireMux_T & _out_back_front_q_io_deq_bits_read & _out_backSel_T[0]
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& _out_out_bits_data_T_1 & _out_back_front_q_io_deq_bits_mask[4])
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& (~_GEN_2 & _GEN_5 & rxCount[3] & rxSync | rxValid);
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end
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end // always @(posedge)
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Queue1_RegMapperInput_i9_m8 out_back_front_q (
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.clock (clock),
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.reset (reset),
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.io_enq_ready (auto_in_a_ready),
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.io_enq_valid (auto_in_a_valid),
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.io_enq_bits_read (auto_in_a_bits_opcode == 3'h4),
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.io_enq_bits_index (auto_in_a_bits_address[11:3]),
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.io_enq_bits_data (auto_in_a_bits_data),
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.io_enq_bits_mask (auto_in_a_bits_mask),
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.io_enq_bits_extra_tlrr_extra_source (auto_in_a_bits_source),
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.io_enq_bits_extra_tlrr_extra_size (auto_in_a_bits_size),
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.io_deq_ready (auto_in_d_ready),
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.io_deq_valid (_out_back_front_q_io_deq_valid),
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.io_deq_bits_read (_out_back_front_q_io_deq_bits_read),
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.io_deq_bits_index (_out_back_front_q_io_deq_bits_index),
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.io_deq_bits_data (_out_back_front_q_io_deq_bits_data),
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.io_deq_bits_mask (_out_back_front_q_io_deq_bits_mask),
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.io_deq_bits_extra_tlrr_extra_source (auto_in_d_bits_source),
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.io_deq_bits_extra_tlrr_extra_size (auto_in_d_bits_size)
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);
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assign auto_in_d_valid = _out_back_front_q_io_deq_valid;
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assign auto_in_d_bits_opcode = {2'h0, _out_back_front_q_io_deq_bits_read};
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assign auto_in_d_bits_data =
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_out_out_bits_data_T_1 ? _GEN[_out_back_front_q_io_deq_bits_index[1:0]] : 64'h0;
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assign auto_txd_out = txReg[0];
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endmodule
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