onur
38 lines
929 B
Systemverilog
38 lines
929 B
Systemverilog
// Generated by CIRCT firtool-1.151.0
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// VCS coverage exclude_file
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module regfile_32x65(
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input [4:0] R0_addr,
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input R0_en,
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R0_clk,
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output [64:0] R0_data,
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input [4:0] R1_addr,
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input R1_en,
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R1_clk,
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output [64:0] R1_data,
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input [4:0] R2_addr,
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input R2_en,
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R2_clk,
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output [64:0] R2_data,
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input [4:0] W0_addr,
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input W0_en,
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W0_clk,
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input [64:0] W0_data,
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input [4:0] W1_addr,
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input W1_en,
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W1_clk,
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input [64:0] W1_data
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);
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reg [64:0] Memory[0:31];
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always @(posedge W0_clk) begin
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if (W0_en)
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Memory[W0_addr] <= W0_data;
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if (W1_en)
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Memory[W1_addr] <= W1_data;
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end // always @(posedge)
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assign R0_data = R0_en ? Memory[R0_addr] : 65'bx;
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assign R1_data = R1_en ? Memory[R1_addr] : 65'bx;
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assign R2_data = R2_en ? Memory[R2_addr] : 65'bx;
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endmodule
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