onur
a25a1a61d0
Add freestanding S25FL256S read/program/erase/verify support and seed a newly formatted ephemeris store with stale records. Age-gate navigation readiness, persist the continuous Toe week, and regenerate the Genesys2 MAX2771 integration and flash image.
79 lines
2.1 KiB
JSON
79 lines
2.1 KiB
JSON
{
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"peripheral" : {
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"displayName" : "max2771-spi.At0x10016000",
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"baseAddress" : "0x10016000",
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"regfields" : [ {
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"command" : {
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"byteOffset" : "0x0",
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"bitOffset" : 0,
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"bitWidth" : 32,
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"name" : "command",
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"description" : "bits[3:0] register address, bit8 read; write starts one 48-clock frame",
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"accessType" : "W"
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}
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}, {
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"write_data" : {
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"byteOffset" : "0x4",
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"bitOffset" : 0,
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"bitWidth" : 32,
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"name" : "write_data",
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"description" : "32-bit MAX2771 register write data",
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"accessType" : "W"
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}
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}, {
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"read_data" : {
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"byteOffset" : "0x8",
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"bitOffset" : 0,
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"bitWidth" : 32,
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"name" : "read_data",
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"description" : "last 32-bit MAX2771 register read data",
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"accessType" : "R"
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}
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}, {
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"status" : {
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"byteOffset" : "0xc",
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"bitOffset" : 0,
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"bitWidth" : 32,
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"name" : "status",
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"description" : "bit0 ready, bit1 busy",
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"accessType" : "R"
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}
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}, {
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"input_clock_hz" : {
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"byteOffset" : "0x10",
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"bitOffset" : 0,
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"bitWidth" : 32,
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"name" : "input_clock_hz",
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"description" : "peripheral input clock frequency",
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"accessType" : "R"
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}
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}, {
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"sclk_hz" : {
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"byteOffset" : "0x14",
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"bitOffset" : 0,
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"bitWidth" : 32,
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"name" : "sclk_hz",
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"description" : "actual integer MAX2771 serial clock frequency",
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"accessType" : "R"
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}
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}, {
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"half_period_cycles" : {
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"byteOffset" : "0x18",
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"bitOffset" : 0,
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"bitWidth" : 32,
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"name" : "half_period_cycles",
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"description" : "input-clock cycles per SCLK half-period",
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"accessType" : "R"
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}
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}, {
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"identification" : {
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"byteOffset" : "0x1c",
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"bitOffset" : 0,
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"bitWidth" : 32,
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"name" : "identification",
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"description" : "ASCII MAX1 peripheral identification",
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"accessType" : "R"
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}
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} ]
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}
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} |