onur
252 lines
7.2 KiB
Systemverilog
252 lines
7.2 KiB
Systemverilog
`timescale 1ns/1ps
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module max2771_spi_engine_case #(
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parameter integer CLOCK_HZ = 50_000_000,
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parameter integer CLOCK_PERIOD_NS = 20,
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parameter integer EXPECTED_HALF_CYCLES = 7
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) (
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output reg done,
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output reg failed
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);
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localparam [31:0] READ_VALUE = 32'hA596_3CC3;
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localparam [31:0] WRITE_VALUE = 32'hBEA4_1603;
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localparam realtime EXPECTED_HALF_NS = CLOCK_PERIOD_NS * EXPECTED_HALF_CYCLES;
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reg clk = 1'b0;
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reg rst_n = 1'b0;
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reg start = 1'b0;
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reg read_not_write = 1'b0;
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reg [3:0] address = 4'd0;
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reg [31:0] write_data = 32'd0;
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wire [31:0] read_data;
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wire busy;
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wire ready;
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wire sclk;
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wire csn;
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wire sdata_i;
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wire sdata_o;
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wire sdata_oe;
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tri sdata;
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reg slave_oe = 1'b0;
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reg slave_data = 1'b0;
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realtime previous_sclk_edge;
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realtime csn_assert_time;
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realtime last_rising_time;
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realtime previous_csn_release;
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integer edge_count;
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assign sdata = sdata_oe ? sdata_o : 1'bz;
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assign sdata = slave_oe ? slave_data : 1'bz;
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assign sdata_i = sdata;
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max2771_spi_engine #(
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.CLOCK_HZ(CLOCK_HZ),
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.MAX_SCLK_HZ(4_000_000)
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) dut (
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.clk(clk),
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.rst_n(rst_n),
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.start(start),
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.read_not_write(read_not_write),
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.address(address),
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.write_data(write_data),
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.read_data(read_data),
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.busy(busy),
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.ready(ready),
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.sclk(sclk),
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.csn(csn),
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.sdata_i(sdata_i),
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.sdata_o(sdata_o),
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.sdata_oe(sdata_oe)
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);
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always #(CLOCK_PERIOD_NS / 2.0) clk = ~clk;
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task automatic fail(input string message);
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begin
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$error("CLOCK_HZ=%0d: %s", CLOCK_HZ, message);
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failed = 1'b1;
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end
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endtask
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task automatic check(input bit condition, input string message);
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begin
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if (!condition)
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fail(message);
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end
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endtask
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task automatic launch(
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input bit is_read,
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input [3:0] register_address,
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input [31:0] value
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);
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begin
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wait (ready);
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@(negedge clk);
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read_not_write = is_read;
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address = register_address;
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write_data = value;
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start = 1'b1;
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@(negedge clk);
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start = 1'b0;
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wait (!csn);
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end
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endtask
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task automatic check_edge_timing(input realtime now_time);
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realtime delta;
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begin
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if (edge_count != 0) begin
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delta = now_time - previous_sclk_edge;
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if (delta != EXPECTED_HALF_NS)
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fail($sformatf("SCLK half-period %0.3f ns, expected %0.3f ns",
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delta, EXPECTED_HALF_NS));
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end
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previous_sclk_edge = now_time;
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edge_count = edge_count + 1;
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end
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endtask
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task automatic run_write;
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reg [47:0] expected_frame;
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integer bit_number;
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begin
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expected_frame = {8'd0, 4'h0, 1'b0, 3'd0, WRITE_VALUE};
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edge_count = 0;
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launch(1'b0, 4'h0, WRITE_VALUE);
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csn_assert_time = $realtime;
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if (previous_csn_release != 0.0)
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check((csn_assert_time - previous_csn_release) >= 100.0,
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"CSN inactive interval is shorter than 100 ns");
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for (bit_number = 0; bit_number < 48; bit_number = bit_number + 1) begin
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@(posedge sclk);
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check_edge_timing($realtime);
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if (bit_number == 0)
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check(($realtime - csn_assert_time) >= 10.0,
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"CSN setup is shorter than 10 ns");
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check(sdata_oe === 1'b1, "host released SDATA during write frame");
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check(sdata === expected_frame[47-bit_number],
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$sformatf("write frame mismatch at bit %0d", bit_number));
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check(sdata !== 1'bx, "SDATA contention detected during write");
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last_rising_time = $realtime;
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@(negedge sclk);
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check_edge_timing($realtime);
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end
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#1;
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check(csn === 1'b1, "CSN did not deassert after 48 clocks");
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check(sdata_oe === 1'b0, "host did not release SDATA after write");
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check(($realtime - 1.0 - last_rising_time) >= 10.0,
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"CSN hold is shorter than 10 ns");
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previous_csn_release = $realtime - 1.0;
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end
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endtask
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task automatic run_read;
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reg [47:0] expected_header;
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integer bit_number;
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begin
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expected_header = {8'd0, 4'h9, 1'b1, 3'd0, 32'd0};
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edge_count = 0;
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launch(1'b1, 4'h9, 32'd0);
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csn_assert_time = $realtime;
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check((csn_assert_time - previous_csn_release) >= 100.0,
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"CSN inactive interval is shorter than 100 ns");
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for (bit_number = 0; bit_number < 48; bit_number = bit_number + 1) begin
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@(posedge sclk);
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check_edge_timing($realtime);
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if (bit_number <= 12) begin
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check(sdata_oe === 1'b1,
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$sformatf("host released SDATA in read header at bit %0d", bit_number));
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check(sdata === expected_header[47-bit_number],
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$sformatf("read header mismatch at bit %0d", bit_number));
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end else if (bit_number <= 15) begin
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check(sdata_oe === 1'b0, "host drove SDATA during turnaround");
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check(slave_oe === 1'b0, "slave drove SDATA during turnaround");
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check(sdata === 1'bz, "SDATA was not high impedance during turnaround");
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end else begin
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check(sdata_oe === 1'b0, "host drove SDATA during read data");
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check(slave_oe === 1'b1, "slave did not drive read data");
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check(sdata === READ_VALUE[47-bit_number],
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$sformatf("read data mismatch at bit %0d", bit_number));
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check(sdata !== 1'bx, "SDATA contention detected during read");
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end
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last_rising_time = $realtime;
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@(negedge sclk);
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check_edge_timing($realtime);
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if ((bit_number >= 15) && (bit_number < 47)) begin
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slave_oe = 1'b1;
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slave_data = READ_VALUE[46-bit_number];
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end
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end
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slave_oe = 1'b0;
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#1;
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check(csn === 1'b1, "CSN did not deassert after read frame");
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check(read_data === READ_VALUE,
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$sformatf("read result 0x%08x, expected 0x%08x", read_data, READ_VALUE));
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check(sdata_oe === 1'b0, "host did not keep SDATA as input after read");
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previous_csn_release = $realtime - 1.0;
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end
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endtask
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initial begin
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done = 1'b0;
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failed = 1'b0;
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previous_csn_release = 0.0;
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repeat (5) @(posedge clk);
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rst_n = 1'b1;
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repeat (2) @(posedge clk);
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check(ready === 1'b1, "engine was not ready after reset");
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check(csn === 1'b1, "CSN was not idle high after reset");
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check(sclk === 1'b0, "SCLK was not idle low after reset");
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check(sdata_oe === 1'b0, "SDATA was not an input after reset");
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run_write();
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run_read();
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done = 1'b1;
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end
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endmodule
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module max2771_spi_engine_tb;
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wire done_50mhz;
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wire failed_50mhz;
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wire done_100mhz;
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wire failed_100mhz;
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max2771_spi_engine_case #(
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.CLOCK_HZ(50_000_000),
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.CLOCK_PERIOD_NS(20),
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.EXPECTED_HALF_CYCLES(7)
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) case_50mhz (
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.done(done_50mhz),
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.failed(failed_50mhz)
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);
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max2771_spi_engine_case #(
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.CLOCK_HZ(100_000_000),
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.CLOCK_PERIOD_NS(10),
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.EXPECTED_HALF_CYCLES(13)
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) case_100mhz (
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.done(done_100mhz),
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.failed(failed_100mhz)
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);
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initial begin
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wait (done_50mhz && done_100mhz);
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if (failed_50mhz || failed_100mhz)
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$fatal(1, "MAX2771 SPI engine test FAILED");
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$display("MAX2771 SPI engine test PASSED: 50 MHz -> 3.571 MHz, 100 MHz -> 3.846 MHz");
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$finish;
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end
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initial begin
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#100_000;
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$fatal(1, "MAX2771 SPI engine test timed out");
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end
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endmodule
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