onur cayan
191 lines
7.8 KiB
Markdown
191 lines
7.8 KiB
Markdown
# Ti375C529 Rocket FPGA flow
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This target keeps the project's RV64 Rocket/GPS subsystem in FPGA fabric and
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replaces only the Xilinx board shell and build flow with Efinix equivalents.
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It does not use the Ti375 hardened RV32 subsystem.
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Detailed porting, synthesis, clocking, JTAG, and verification notes are in
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[`flow/efinity/README.md`](flow/efinity/README.md).
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## Build and program
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```bash
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make FPGA_BOARD=ti375c529 fpga-config
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make FPGA_BOARD=ti375c529 fpga-rtl
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make FPGA_BOARD=ti375c529 fpga-bitstream
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make FPGA_BOARD=ti375c529 fpga-program
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```
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The Makefile auto-discovers versioned Efinity installations under
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`/tools/efinix/efinity`, `/tools/Efinix/efinity`, `/opt`, the current user's
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home directory, and `tools/local/efinity`. Override discovery when required:
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```bash
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make FPGA_BOARD=ti375c529 fpga-bitstream \
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EFINITY_HOME=/path/to/efinity/<version>
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```
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`fpga-rtl` does not require Efinity. The `interface`, `bitstream`, and
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programming targets require a complete Efinity installation containing
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`bin/setup.sh` and `scripts/efx_run.py`; they now stop before hardware
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elaboration with a direct diagnostic when it is absent.
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Concurrent Ti375 `map` or `bitstream` invocations are rejected because they
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share generated FIRRTL, SystemVerilog, and Efinity work directories.
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Efinity is run with unbuffered Python output so `map`, `pnr`, and `pgm`
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progress remains visible in the terminal and `out/logs/full.log`.
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Programming auto-selects the connected Ti375 development kit. If more than
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one compatible FTDI device is attached, run `make FPGA_BOARD=ti375c529
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fpga-detect` to list the bus-qualified URLs and pass the selected one as
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`FTDI_URL=...`.
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Volatile JTAG programming and GDB loading into Rocket DTIM remain available.
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Persistent boot uses the board's Lower 512-Mbit SPI flash with this map:
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| Region | Flash offset | Contents |
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|---|---:|---|
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| FPGA configuration | `0x00000000` | Efinity active-mode configuration HEX |
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| Rocket application | `0x00800000` | Boot header and ELF-derived payload |
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| Navigation context | `0x03FC0000` | Two 64-KiB journal sectors |
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| Ephemeris cache | `0x03FE0000` | Two 64-KiB journal sectors |
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The application starts at 8 MiB because the compressed Ti375 configuration is
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currently about 5.19 MB; the previous 4 MiB trial offset would overlap it.
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Generate or program the Efinity raw HEX images with:
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```bash
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make FPGA_BOARD=ti375c529 fpga-mcs APP=hello_uart
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make FPGA_BOARD=ti375c529 fpga-flash-app APP=hello_uart
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make FPGA_BOARD=ti375c529 fpga-flash-bitstream
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make FPGA_BOARD=ti375c529 fpga-flash-mcs APP=hello_uart
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```
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`fpga-mcs` is the repository-wide compatibility target name. For this Efinix
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board it produces `.hex`, not Xilinx `.mcs`. `fpga-flash-app` changes only the
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application region; `fpga-flash-mcs` erases/programs configuration plus the
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application through Efinity's pre-built JTAG-to-SPI bridge and verifies the
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readback. Cold boot from this layout was verified by a complete board power
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cycle: Ti375 configured from flash and Rocket loaded and completed
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`hello_uart` from the application region without a JTAG/GDB load.
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## Debug and load
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Use the host OpenOCD build, not the OpenOCD shipped with Efinity. The build
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must include `riscv set_bscan_tunnel_ir`; Ti375 uses a 5-bit outer TAP and
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selects `JTAG_USER1` with instruction `0x08`.
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OpenOCD 0.12 can be given that upstream-compatible command with
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`flow/debug/openocd-0.12-ti375-bscan.patch`.
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Apply it from a clean OpenOCD 0.12 source tree before configuring and building
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the host tool:
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```bash
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git apply --check /path/to/gps/targets/fpga/ti375c529/flow/debug/openocd-0.12-ti375-bscan.patch
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git apply /path/to/gps/targets/fpga/ti375c529/flow/debug/openocd-0.12-ti375-bscan.patch
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```
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Place the resulting `openocd` in `PATH`, or pass its absolute path with
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`OPENOCD=/path/to/openocd`.
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In one terminal:
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```bash
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make FPGA_BOARD=ti375c529 fpga-debug-openocd
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```
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In a second terminal:
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```bash
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make FPGA_BOARD=ti375c529 fpga-debug-load APP=hello_uart
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make FPGA_BOARD=ti375c529 fpga-uart
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```
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The target deliberately selects `/tools/toolchain/bin/riscv64-unknown-elf-gdb`
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when it exists. The medany compiler toolchain is still used to build software,
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but it is not expected to contain GDB.
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Efinity 2025.2 leaves Rocket's block-local packed store-data array undriven
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(`VDB-1002`). `tools/prepare_efinity_rtl.py` rewrites that generated RTL
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expression as an equivalent explicit `case`. Without the rewrite, DMI itself
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works, but GPR/CSR values stored into Debug Module data registers read as zero;
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OpenOCD consequently reports a misleading `misa=0`.
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The patch is deliberately post-generation: Chisel and `firtool` first emit the
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Ti375 SystemVerilog tree, then `prepare_efinity_rtl.py` modifies only the
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generated Ti375 `Rocket.sv` before Efinity synthesis. It does not edit Rocket's
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native/upstream Chisel sources.
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Two equivalent four-entry packed temporaries in the generated pbus/cbus
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`TLAtomicAutomata` modules are rewritten for the same reason, preserving the
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four atomic-operation mappings while removing their `VDB-1002` risk.
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The same script generates Ti375-only copies of the acquisition carrier NCO,
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tracking carrier NCO, and FFT twiddle ROM under
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`out/build/generated/gps_efinity/`. This avoids Efinity 2025.2
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whole-array/`initial`/`$sin` elaboration failures without editing the shared GPS
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RTL. Only the Ti375 source list selects these copies; Genesys2 and VCU118 still
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use the originals. Detailed source paths, warning interpretation, and Questa
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RTL/post-map equivalence results are in the Efinity flow notes.
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The affected generated source is
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`hardware/generated/ti375c529-soc-verilog/Rocket.sv`; Efinity records the
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original diagnostic in
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`targets/fpga/ti375c529/flow/efinity/outflow/ti375c529_rocket.warn.log`.
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The checked-in repair is
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`targets/fpga/ti375c529/tools/prepare_efinity_rtl.py` and runs after every
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`firtool` invocation, before Efinity synthesis.
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## Board connections
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PMOD0/J13 carries the GPS RF sampler:
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| Signal | PMOD pin | FPGA resource | Package pin |
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| `rf_clk` | 10 | GPIOR_95_CLK12 | A12 |
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| `rf_data[0]` | 2 | GPIOR_89 | G16 |
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| `rf_data[1]` | 3 | GPIOR_90 | F16 |
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| `rf_data[2]` | 4 | GPIOR_91 | F17 |
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| `rf_data[3]` | 7 | GPIOR_92 | G17 |
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| `max2771_spi_sclk` | 1 | GPIOR_88_PLLIN1 | G15 |
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| `max2771_spi_csn` | 8 | GPIOR_93_PLLIN1 | A11 |
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| `max2771_spi_sdata` | 9 | GPIOR_94 | A13 |
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`rf_clk` must be wired to J13 pin 10. Pin 10 is the PMOD0 header's dedicated
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3.3 V global-clock input. J13 pin 1 is used as the MAX2771 serial clock output;
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using it as the raw AFE clock would make Efinity promote normal GPIO routing
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into a GBUF and issue an extra-clock-insertion-delay warning.
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As on Genesys2 and VCU118, the AX2771 clock is both the raw AFE sample clock
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and the source of the GPS processing-clock chain. Two Titanium PLLs generate
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an intermediate 55.5556 MHz clock, then 100 MHz acquisition and 125 MHz
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tracking clocks. The Rocket fabric uses the independent on-board 100 MHz
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oscillator.
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PMOD1/J14 carries the sensor SPI, interrupt, and PPS:
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| Signal | PMOD pin | FPGA resource | Package pin |
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| `pmod_spi_csn` | 1 | GPIOR_96_CLK13 | B12 |
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| `pmod_spi_dq[0]` | 2 | GPIOR_97 | C14 |
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| `pmod_spi_dq[1]` | 3 | GPIOR_98 | C13 |
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| `pmod_spi_sck` | 4 | GPIOR_99 | C12 |
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| `pmod_spi_dq[2]` | 7 | GPIOR_100 | D12 |
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| `pmod_spi_dq[3]` | 8 | GPIOR_101_PLLIN1 | F12 |
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| `pmod_irq` | 9 | GPIOR_102 | D13 |
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| `gps_pps` | 10 | GPIOR_103 | E13 |
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The FTDI UART is `/dev/ttyUSB2` on the current Linux enumeration. SW3 is the
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active-low Rocket reset. JTAG uses Efinix `JTAG_USER1` and the existing Rocket
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DMI tunnel protocol.
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The Lower flash user-mode connection is internal to the development kit:
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| Signal | FPGA resource | Package pin |
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| `flash_csn` | GPIOB_N_38 / SSL_N | A7 |
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| `flash_sck` | GPIOB_P_39 / CCK | G6 |
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| `flash_dq[0]` | GPIOB_N_40 / CDI0 | H4 |
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| `flash_dq[1]` | GPIOB_P_40 / CDI1 | H5 |
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| `flash_dq[2]` | GPIOB_N_39 / CDI2 | G5 |
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| `flash_dq[3]` | GPIOB_P_38 / CDI3 | B7 |
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