141 lines
4.3 KiB
Markdown
141 lines
4.3 KiB
Markdown
# Ethernet RF Stream
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Raw Ethernet is used directly. There is no IP, UDP, or TCP layer.
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This directory contains the shared host sender and the original VCU118 Ethernet
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RF integration notes. Build the selected board bitstream with
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`RF_INPUT_MODE=ethernet`; the default `RF_INPUT_MODE=pmod` removes the Ethernet
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RF IP/RTL from the FPGA top.
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Default host command using the C sender:
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```sh
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sudo make -C targets/fpga/vcu118 eth-rf-send
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sudo make -C targets/fpga/genesys2 eth-rf-send
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```
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Python fallback:
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```sh
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sudo make -C targets/fpga/vcu118 eth-rf-send-python
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sudo make -C targets/fpga/genesys2 eth-rf-send-python
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```
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## SignalSim REAL4 generation
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Generate single-channel real IF data from SignalSim. The file name may still
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contain `iq`, but the `.tag` file must show `IQ = 0`.
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SignalSim settings:
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```text
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Format: REAL4
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Sample MHz: 16.368
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Desired IF MHz: 4.092
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RF/LO Center MHz: 1571.328
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Signal: GPS L1 C/A
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```
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GPS L1 is `1575.420 MHz`, so:
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```text
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1575.420 - 1571.328 = 4.092 MHz
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```
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Expected tag:
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```text
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FMT = INT4
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F_S = 16.368000
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F_LO = 1571.328000
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IQ = 0
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BITS = 4
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```
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Do not use `RF/LO Center MHz = 1571.420` for this flow. That puts GPS L1 at
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`4.000 MHz` IF, while the current acquisition RTL is centered around
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`4.092 MHz`.
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Stream the generated `REAL4` file with sign/magnitude conversion:
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```sh
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sudo make -C targets/fpga/vcu118 eth-rf-send \
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ETH_RF_INPUT=/path/to/globsky_if_iq4.bin \
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ETH_RF_SAMPLE_FORMAT=real4-signmag
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```
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## Existing CATI RF dumps
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`/path/to/aa_july_cati2.bin` is not packed two-samples-per-byte
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SignalSim REAL4 data. Its bytes carry one 4-bit sample in the low nibble, so
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stream it as `raw-low4`:
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```sh
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sudo make -C targets/fpga/vcu118 eth-rf-send \
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ETH_RF_INPUT=/path/to/aa_july_cati2.bin \
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ETH_RF_SAMPLE_FORMAT=raw-low4
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```
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Do not use `real4-signmag` for this file. That format splits each input byte
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into two nibbles and inserts the zero high nibble as an extra RF sample, which
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breaks acquisition/tracking.
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Useful overrides:
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```sh
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sudo make -C targets/fpga/vcu118 eth-rf-send \
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ETH_RF_IFACE=enx14ebb6850432 \
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ETH_RF_INPUT=/path/to/globsky_if_iq4.bin \
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ETH_RF_SAMPLE_FORMAT=real4-signmag
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```
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For a Globsky `REAL8` output:
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```sh
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sudo make -C targets/fpga/vcu118 eth-rf-send \
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ETH_RF_IFACE=enx14ebb6850432 \
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ETH_RF_INPUT=/path/to/globsky_if_iq8.bin \
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ETH_RF_SAMPLE_FORMAT=real8-to-4
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```
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Short link test:
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```sh
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sudo make -C targets/fpga/vcu118 eth-rf-send ETH_RF_MAX_SAMPLES=1000000
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```
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The default format treats the file as packed real 4-bit SignalSim samples. The Globsky file name may contain `iq`, but the `.tag` file is authoritative: use `real4-signmag` for SignalSim `FMT = INT4, IQ = 0` and `real8-to-4` for `FMT = INT8, IQ = 0`. The FPGA sends an ACK for every frame with FIFO credit. If the FIFO is near full, the host retries the same frame instead of advancing the file offset.
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The RF port consumes one 4-bit sample per `16.368 MHz` clock:
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```text
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16.368 Msps * 4 bits = 65.472 Mbps = 8.184 MB/s
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```
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The host uses the C sender, jumbo raw Ethernet frames by default (`ETH_RF_MTU=9000`, `ETH_RF_CHUNK_SAMPLES=17800`), and preloads the FPGA FIFO before sending START (`ETH_RF_PRELOAD_SAMPLES=131072`). With 1500 MTU and 2800-sample chunks, Python had to wait for an ACK on too many small frames and measured about `10.3 Msps`, which is not enough for continuous `16.368 Msps` playback.
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Measured short C test:
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```text
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rate=16.397 Msps rf=65.589 Mbps 8.199 MB/s
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min_fifo_level=71200 no_space=2808
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```
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`no_space` means the host was faster than the FPGA consumer and retried when the FIFO was near full; it is backpressure, not dropped data.
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Supported `ETH_RF_SAMPLE_FORMAT` values:
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- `real4-packed`: packed real 4-bit samples, two samples per byte, high nibble first.
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- `real4-signmag`: SignalSim/PocketSDR-style packed real 4-bit sign+magnitude samples converted to signed 4-bit two's complement.
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- `real8-to-4`: signed 8-bit real samples converted to 4-bit signed samples.
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- `raw-low4`: one 4-bit sample in each input byte's low nibble.
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- `raw-high4`: one 4-bit sample in each input byte's high nibble.
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- `packed-high-first`: two samples per byte, high nibble first.
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- `packed-low-first`: two samples per byte, low nibble first in the file and converted on the wire.
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FPGA defaults:
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- Local MAC: `02:00:00:00:10:89`
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- EtherType: `0x88B6`
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- RF sample clock: `16.368 MHz`
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