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gps/hardware/fpga/vcu118/constraints/vcu118_max2771_spi.xdc
T
2026-08-06 22:14:52 +03:00

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## MAX2771 dedicated three-wire serial interface on unused PMOD0/J52 pins.
## PMOD0_0..4 remain assigned to GPS RF. U41 level-shifts the connector's
## 3.3 V signals to the FPGA bank's 1.8 V I/O.
##
## max2771_spi_sclk PMOD0_5 J52.4
## max2771_spi_csn PMOD0_6 J52.6
## max2771_spi_sdata PMOD0_7 J52.8 (bidirectional)
set_property PACKAGE_PIN AU16 [get_ports max2771_spi_sclk]
set_property PACKAGE_PIN AT15 [get_ports max2771_spi_csn]
set_property PACKAGE_PIN AT16 [get_ports max2771_spi_sdata]
set_property IOSTANDARD LVCMOS18 [get_ports {max2771_spi_sclk max2771_spi_csn max2771_spi_sdata}]
set_property DRIVE 8 [get_ports {max2771_spi_sclk max2771_spi_csn max2771_spi_sdata}]
set_property SLEW SLOW [get_ports {max2771_spi_sclk max2771_spi_csn max2771_spi_sdata}]