onur
111 lines
3.4 KiB
Systemverilog
111 lines
3.4 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module AsyncQueueSink_DebugInternalBundle(
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input clock,
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reset,
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output io_deq_valid,
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io_deq_bits_resumereq,
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output [9:0] io_deq_bits_hartsel,
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output io_deq_bits_ackhavereset,
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io_deq_bits_hrmask_0,
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input io_async_mem_0_resumereq,
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input [9:0] io_async_mem_0_hartsel,
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input io_async_mem_0_ackhavereset,
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io_async_mem_0_hrmask_0,
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output io_async_ridx,
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input io_async_widx,
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output io_async_safe_ridx_valid,
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input io_async_safe_widx_valid,
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io_async_safe_source_reset_n,
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output io_async_safe_sink_reset_n
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);
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wire io_deq_valid_0;
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wire _source_valid_io_out;
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wire _source_extend_io_out;
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wire _sink_valid_0_io_out;
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wire [14:0] _io_deq_bits_deq_bits_reg_io_q;
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wire _widx_widx_gray_io_q;
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reg ridx_ridx_bin;
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wire ridx = _source_valid_io_out & ridx_ridx_bin + io_deq_valid_0;
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wire valid = _source_valid_io_out & ridx != _widx_widx_gray_io_q;
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reg valid_reg;
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assign io_deq_valid_0 = valid_reg & _source_valid_io_out;
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reg ridx_gray;
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always @(posedge clock or posedge reset) begin
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if (reset) begin
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ridx_ridx_bin <= 1'h0;
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valid_reg <= 1'h0;
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ridx_gray <= 1'h0;
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end
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else begin
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ridx_ridx_bin <= ridx;
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valid_reg <= valid;
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ridx_gray <= ridx;
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end
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end // always @(posedge, posedge)
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`ifdef ENABLE_INITIAL_REG_
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`ifdef FIRRTL_BEFORE_INITIAL
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`FIRRTL_BEFORE_INITIAL
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`endif // FIRRTL_BEFORE_INITIAL
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initial begin
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if (reset) begin
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ridx_ridx_bin = 1'h0;
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valid_reg = 1'h0;
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ridx_gray = 1'h0;
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end
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end // initial
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`ifdef FIRRTL_AFTER_INITIAL
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`FIRRTL_AFTER_INITIAL
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`endif // FIRRTL_AFTER_INITIAL
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`endif // ENABLE_INITIAL_REG_
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AsyncResetSynchronizerShiftReg_w1_d3_i0 widx_widx_gray (
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.clock (clock),
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.reset (reset),
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.io_d (io_async_widx),
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.io_q (_widx_widx_gray_io_q)
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);
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ClockCrossingReg_w15 io_deq_bits_deq_bits_reg (
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.clock (clock),
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.io_d
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({io_async_mem_0_resumereq,
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io_async_mem_0_hartsel,
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io_async_mem_0_ackhavereset,
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2'h0,
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io_async_mem_0_hrmask_0}),
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.io_q (_io_deq_bits_deq_bits_reg_io_q),
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.io_en (valid)
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);
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AsyncValidSync sink_valid_0 (
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.io_in (1'h1),
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.io_out (_sink_valid_0_io_out),
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.clock (clock),
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.reset (reset | ~io_async_safe_source_reset_n)
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);
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AsyncValidSync sink_valid_1 (
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.io_in (_sink_valid_0_io_out),
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.io_out (io_async_safe_ridx_valid),
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.clock (clock),
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.reset (reset | ~io_async_safe_source_reset_n)
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);
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AsyncValidSync source_extend (
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.io_in (io_async_safe_widx_valid),
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.io_out (_source_extend_io_out),
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.clock (clock),
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.reset (reset | ~io_async_safe_source_reset_n)
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);
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AsyncValidSync source_valid (
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.io_in (_source_extend_io_out),
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.io_out (_source_valid_io_out),
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.clock (clock),
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.reset (reset)
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);
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assign io_deq_valid = io_deq_valid_0;
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assign io_deq_bits_resumereq = _io_deq_bits_deq_bits_reg_io_q[14];
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assign io_deq_bits_hartsel = _io_deq_bits_deq_bits_reg_io_q[13:4];
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assign io_deq_bits_ackhavereset = _io_deq_bits_deq_bits_reg_io_q[3];
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assign io_deq_bits_hrmask_0 = _io_deq_bits_deq_bits_reg_io_q[0];
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assign io_async_ridx = ridx_gray;
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assign io_async_safe_sink_reset_n = ~reset;
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endmodule
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