onur
17 lines
293 B
Systemverilog
17 lines
293 B
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module AsyncValidSync(
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input io_in,
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output io_out,
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input clock,
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reset
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);
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AsyncResetSynchronizerShiftReg_w1_d3_i0_1 io_out_source_valid_0 (
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.clock (clock),
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.reset (reset),
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.io_d (io_in),
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.io_q (io_out)
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);
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endmodule
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