onur
106 lines
4.8 KiB
Systemverilog
106 lines
4.8 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module CLINT(
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input clock,
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reset,
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output auto_int_out_0,
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auto_int_out_1,
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auto_in_a_ready,
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input auto_in_a_valid,
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input [2:0] auto_in_a_bits_opcode,
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input [1:0] auto_in_a_bits_size,
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input [5:0] auto_in_a_bits_source,
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input [25:0] auto_in_a_bits_address,
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input [7:0] auto_in_a_bits_mask,
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input [63:0] auto_in_a_bits_data,
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input auto_in_d_ready,
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output auto_in_d_valid,
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output [2:0] auto_in_d_bits_opcode,
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output [1:0] auto_in_d_bits_size,
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output [5:0] auto_in_d_bits_source,
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output [63:0] auto_in_d_bits_data,
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input io_rtcTick
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);
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wire out_woready_9;
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wire out_woready_17;
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reg [63:0] time_0;
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reg [63:0] timecmp_0;
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reg ipi_0;
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wire _out_out_bits_data_WIRE_1 = auto_in_a_bits_address[13:3] == 11'h0;
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wire _out_out_bits_data_WIRE_2 = &(auto_in_a_bits_address[13:3]);
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wire valids_1_0 = out_woready_9 & auto_in_a_bits_mask[0];
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wire valids_1_1 = out_woready_9 & auto_in_a_bits_mask[1];
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wire valids_1_2 = out_woready_9 & auto_in_a_bits_mask[2];
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wire valids_1_3 = out_woready_9 & auto_in_a_bits_mask[3];
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wire valids_1_4 = out_woready_9 & auto_in_a_bits_mask[4];
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wire valids_1_5 = out_woready_9 & auto_in_a_bits_mask[5];
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wire valids_1_6 = out_woready_9 & auto_in_a_bits_mask[6];
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wire valids_1_7 = out_woready_9 & auto_in_a_bits_mask[7];
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wire valids_0 = out_woready_17 & auto_in_a_bits_mask[0];
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wire valids_1 = out_woready_17 & auto_in_a_bits_mask[1];
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wire valids_2 = out_woready_17 & auto_in_a_bits_mask[2];
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wire valids_3 = out_woready_17 & auto_in_a_bits_mask[3];
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wire valids_4 = out_woready_17 & auto_in_a_bits_mask[4];
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wire valids_5 = out_woready_17 & auto_in_a_bits_mask[5];
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wire valids_6 = out_woready_17 & auto_in_a_bits_mask[6];
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wire valids_7 = out_woready_17 & auto_in_a_bits_mask[7];
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wire [3:0] _out_backSel_T = 4'h1 << auto_in_a_bits_address[15:14];
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wire _out_wofireMux_T_2 =
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auto_in_a_valid & auto_in_d_ready & auto_in_a_bits_opcode != 3'h4;
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assign out_woready_17 =
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_out_wofireMux_T_2 & _out_backSel_T[1] & _out_out_bits_data_WIRE_1;
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assign out_woready_9 =
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_out_wofireMux_T_2 & _out_backSel_T[2] & _out_out_bits_data_WIRE_2;
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wire [3:0] _GEN =
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{{1'h1},
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{_out_out_bits_data_WIRE_2},
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{_out_out_bits_data_WIRE_1},
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{_out_out_bits_data_WIRE_1}};
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wire [3:0][63:0] _GEN_0 = {{64'h0}, {time_0}, {timecmp_0}, {{63'h0, ipi_0}}};
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always @(posedge clock) begin
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if (reset) begin
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time_0 <= 64'h0;
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ipi_0 <= 1'h0;
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end
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else begin
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if (valids_1_0 | valids_1_1 | valids_1_2 | valids_1_3 | valids_1_4 | valids_1_5
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| valids_1_6 | valids_1_7)
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time_0 <=
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{valids_1_7 ? auto_in_a_bits_data[63:56] : time_0[63:56],
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valids_1_6 ? auto_in_a_bits_data[55:48] : time_0[55:48],
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valids_1_5 ? auto_in_a_bits_data[47:40] : time_0[47:40],
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valids_1_4 ? auto_in_a_bits_data[39:32] : time_0[39:32],
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valids_1_3 ? auto_in_a_bits_data[31:24] : time_0[31:24],
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valids_1_2 ? auto_in_a_bits_data[23:16] : time_0[23:16],
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valids_1_1 ? auto_in_a_bits_data[15:8] : time_0[15:8],
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valids_1_0 ? auto_in_a_bits_data[7:0] : time_0[7:0]};
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else if (io_rtcTick)
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time_0 <= time_0 + 64'h1;
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if (_out_wofireMux_T_2 & _out_backSel_T[0] & _out_out_bits_data_WIRE_1
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& auto_in_a_bits_mask[0])
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ipi_0 <= auto_in_a_bits_data[0];
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end
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if (valids_0 | valids_1 | valids_2 | valids_3 | valids_4 | valids_5 | valids_6
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| valids_7)
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timecmp_0 <=
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{valids_7 ? auto_in_a_bits_data[63:56] : timecmp_0[63:56],
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valids_6 ? auto_in_a_bits_data[55:48] : timecmp_0[55:48],
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valids_5 ? auto_in_a_bits_data[47:40] : timecmp_0[47:40],
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valids_4 ? auto_in_a_bits_data[39:32] : timecmp_0[39:32],
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valids_3 ? auto_in_a_bits_data[31:24] : timecmp_0[31:24],
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valids_2 ? auto_in_a_bits_data[23:16] : timecmp_0[23:16],
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valids_1 ? auto_in_a_bits_data[15:8] : timecmp_0[15:8],
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valids_0 ? auto_in_a_bits_data[7:0] : timecmp_0[7:0]};
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end // always @(posedge)
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assign auto_int_out_0 = ipi_0;
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assign auto_int_out_1 = time_0 >= timecmp_0;
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assign auto_in_a_ready = auto_in_d_ready;
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assign auto_in_d_valid = auto_in_a_valid;
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assign auto_in_d_bits_opcode = {2'h0, auto_in_a_bits_opcode == 3'h4};
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assign auto_in_d_bits_size = auto_in_a_bits_size;
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assign auto_in_d_bits_source = auto_in_a_bits_source;
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assign auto_in_d_bits_data =
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_GEN[auto_in_a_bits_address[15:14]] ? _GEN_0[auto_in_a_bits_address[15:14]] : 64'h0;
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endmodule
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