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gps/hardware/generated/genesys2-soc-verilog/ClockGroup.sv
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2026-08-06 22:14:52 +03:00

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Systemverilog

// Generated by CIRCT firtool-1.151.0
module ClockGroup(
input auto_in_member_sbus_0_clock,
auto_in_member_sbus_0_reset,
output auto_out_clock,
auto_out_reset
);
assign auto_out_clock = auto_in_member_sbus_0_clock;
assign auto_out_reset = auto_in_member_sbus_0_reset;
endmodule