onur
1246 lines
65 KiB
Systemverilog
1246 lines
65 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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// Users can define 'PRINTF_COND' to add an extra gate to prints.
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`ifndef PRINTF_COND_
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`ifdef PRINTF_COND
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`define PRINTF_COND_ (`PRINTF_COND)
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`else // PRINTF_COND
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`define PRINTF_COND_ 1
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`endif // PRINTF_COND
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`endif // not def PRINTF_COND_
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module DCache(
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input clock,
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reset,
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auto_out_a_ready,
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output auto_out_a_valid,
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output [2:0] auto_out_a_bits_opcode,
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auto_out_a_bits_param,
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output [3:0] auto_out_a_bits_size,
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output [31:0] auto_out_a_bits_address,
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output auto_out_a_bits_user_amba_prot_bufferable,
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auto_out_a_bits_user_amba_prot_modifiable,
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auto_out_a_bits_user_amba_prot_readalloc,
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auto_out_a_bits_user_amba_prot_writealloc,
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auto_out_a_bits_user_amba_prot_privileged,
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output [7:0] auto_out_a_bits_mask,
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output [63:0] auto_out_a_bits_data,
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output auto_out_d_ready,
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input auto_out_d_valid,
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input [2:0] auto_out_d_bits_opcode,
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input [3:0] auto_out_d_bits_size,
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input auto_out_d_bits_denied,
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input [63:0] auto_out_d_bits_data,
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output io_cpu_req_ready,
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input io_cpu_req_valid,
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input [33:0] io_cpu_req_bits_addr,
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input [6:0] io_cpu_req_bits_tag,
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input [4:0] io_cpu_req_bits_cmd,
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input [1:0] io_cpu_req_bits_size,
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input io_cpu_req_bits_signed,
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input [1:0] io_cpu_req_bits_dprv,
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input io_cpu_req_bits_no_xcpt,
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io_cpu_s1_kill,
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input [63:0] io_cpu_s1_data_data,
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input [7:0] io_cpu_s1_data_mask,
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output io_cpu_s2_nack,
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io_cpu_resp_valid,
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output [6:0] io_cpu_resp_bits_tag,
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output [1:0] io_cpu_resp_bits_size,
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output [63:0] io_cpu_resp_bits_data,
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output io_cpu_resp_bits_replay,
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io_cpu_resp_bits_has_data,
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output [63:0] io_cpu_resp_bits_data_word_bypass,
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io_cpu_resp_bits_data_raw,
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output io_cpu_replay_next,
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io_cpu_s2_xcpt_ma_ld,
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io_cpu_s2_xcpt_ma_st,
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io_cpu_s2_xcpt_pf_ld,
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io_cpu_s2_xcpt_pf_st,
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io_cpu_s2_xcpt_ae_ld,
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io_cpu_s2_xcpt_ae_st,
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io_cpu_ordered,
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io_cpu_perf_grant,
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input io_ptw_status_debug,
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io_ptw_pmp_0_cfg_l,
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input [1:0] io_ptw_pmp_0_cfg_a,
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input io_ptw_pmp_0_cfg_w,
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io_ptw_pmp_0_cfg_r,
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input [29:0] io_ptw_pmp_0_addr,
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input [31:0] io_ptw_pmp_0_mask,
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input io_ptw_pmp_1_cfg_l,
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input [1:0] io_ptw_pmp_1_cfg_a,
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input io_ptw_pmp_1_cfg_w,
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io_ptw_pmp_1_cfg_r,
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input [29:0] io_ptw_pmp_1_addr,
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input [31:0] io_ptw_pmp_1_mask,
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input io_ptw_pmp_2_cfg_l,
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input [1:0] io_ptw_pmp_2_cfg_a,
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input io_ptw_pmp_2_cfg_w,
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io_ptw_pmp_2_cfg_r,
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input [29:0] io_ptw_pmp_2_addr,
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input [31:0] io_ptw_pmp_2_mask,
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input io_ptw_pmp_3_cfg_l,
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input [1:0] io_ptw_pmp_3_cfg_a,
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input io_ptw_pmp_3_cfg_w,
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io_ptw_pmp_3_cfg_r,
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input [29:0] io_ptw_pmp_3_addr,
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input [31:0] io_ptw_pmp_3_mask,
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input io_ptw_pmp_4_cfg_l,
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input [1:0] io_ptw_pmp_4_cfg_a,
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input io_ptw_pmp_4_cfg_w,
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io_ptw_pmp_4_cfg_r,
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input [29:0] io_ptw_pmp_4_addr,
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input [31:0] io_ptw_pmp_4_mask,
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input io_ptw_pmp_5_cfg_l,
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input [1:0] io_ptw_pmp_5_cfg_a,
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input io_ptw_pmp_5_cfg_w,
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io_ptw_pmp_5_cfg_r,
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input [29:0] io_ptw_pmp_5_addr,
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input [31:0] io_ptw_pmp_5_mask,
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input io_ptw_pmp_6_cfg_l,
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input [1:0] io_ptw_pmp_6_cfg_a,
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input io_ptw_pmp_6_cfg_w,
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io_ptw_pmp_6_cfg_r,
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input [29:0] io_ptw_pmp_6_addr,
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input [31:0] io_ptw_pmp_6_mask,
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input io_ptw_pmp_7_cfg_l,
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input [1:0] io_ptw_pmp_7_cfg_a,
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input io_ptw_pmp_7_cfg_w,
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io_ptw_pmp_7_cfg_r,
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input [29:0] io_ptw_pmp_7_addr,
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input [31:0] io_ptw_pmp_7_mask
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);
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wire io_cpu_s2_xcpt_ma_st_0;
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wire io_cpu_s2_xcpt_ma_ld_0;
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wire io_cpu_s2_xcpt_ae_st_0;
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wire io_cpu_s2_xcpt_ae_ld_0;
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wire io_cpu_s2_xcpt_pf_st_0;
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wire io_cpu_s2_xcpt_pf_ld_0;
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wire _GEN;
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wire s1_nack;
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wire [63:0] _amoalus_0_io_out_unmasked;
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wire _dataArb_io_in_1_ready;
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wire _dataArb_io_in_3_ready;
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wire _dataArb_io_out_valid;
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wire [19:0] _dataArb_io_out_bits_addr;
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wire _dataArb_io_out_bits_write;
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wire [63:0] _dataArb_io_out_bits_wdata;
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wire [7:0] _dataArb_io_out_bits_eccMask;
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wire [63:0] _data_io_resp_0;
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wire _metaArb_io_in_7_ready;
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wire _metaArb_io_out_valid;
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wire _metaArb_io_out_bits_write;
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wire [33:0] _metaArb_io_out_bits_addr;
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wire [31:0] _tlb_io_resp_paddr;
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wire _tlb_io_resp_pf_ld;
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wire _tlb_io_resp_pf_st;
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wire _tlb_io_resp_ae_ld;
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wire _tlb_io_resp_ae_st;
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wire _tlb_io_resp_ma_ld;
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wire _tlb_io_resp_ma_st;
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wire _tlb_io_resp_cacheable;
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reg s1_valid;
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wire s1_valid_masked = s1_valid & ~io_cpu_s1_kill;
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reg [33:0] s1_req_addr;
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reg [6:0] s1_req_tag;
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reg [4:0] s1_req_cmd;
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reg [1:0] s1_req_size;
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reg s1_req_signed;
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reg [1:0] s1_req_dprv;
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reg s1_req_no_xcpt;
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reg [33:0] s1_tlb_req_vaddr;
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reg [1:0] s1_tlb_req_size;
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reg [4:0] s1_tlb_req_cmd;
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reg [1:0] s1_tlb_req_prv;
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wire _io_cpu_perf_canAcceptLoadThenLoad_T_1 = s1_req_cmd == 5'h0;
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wire _io_cpu_perf_canAcceptLoadThenLoad_T_2 = s1_req_cmd == 5'h10;
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wire _io_cpu_perf_canAcceptLoadThenLoad_T_3 = s1_req_cmd == 5'h6;
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wire _io_cpu_perf_canAcceptLoadThenLoad_T_29 = s1_req_cmd == 5'h7;
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wire _io_cpu_perf_canAcceptLoadThenLoad_T_31 = s1_req_cmd == 5'h4;
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wire _io_cpu_perf_canAcceptLoadThenLoad_T_32 = s1_req_cmd == 5'h9;
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wire _io_cpu_perf_canAcceptLoadThenLoad_T_33 = s1_req_cmd == 5'hA;
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wire _io_cpu_perf_canAcceptLoadThenLoad_T_34 = s1_req_cmd == 5'hB;
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wire _io_cpu_perf_canAcceptLoadThenLoad_T_38 = s1_req_cmd == 5'h8;
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wire _io_cpu_perf_canAcceptLoadThenLoad_T_39 = s1_req_cmd == 5'hC;
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wire _io_cpu_perf_canAcceptLoadThenLoad_T_40 = s1_req_cmd == 5'hD;
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wire _io_cpu_perf_canAcceptLoadThenLoad_T_41 = s1_req_cmd == 5'hE;
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wire _io_cpu_perf_canAcceptLoadThenLoad_T_42 = s1_req_cmd == 5'hF;
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wire s1_read =
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_io_cpu_perf_canAcceptLoadThenLoad_T_1 | _io_cpu_perf_canAcceptLoadThenLoad_T_2
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| _io_cpu_perf_canAcceptLoadThenLoad_T_3 | _io_cpu_perf_canAcceptLoadThenLoad_T_29
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| _io_cpu_perf_canAcceptLoadThenLoad_T_31 | _io_cpu_perf_canAcceptLoadThenLoad_T_32
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| _io_cpu_perf_canAcceptLoadThenLoad_T_33 | _io_cpu_perf_canAcceptLoadThenLoad_T_34
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| _io_cpu_perf_canAcceptLoadThenLoad_T_38 | _io_cpu_perf_canAcceptLoadThenLoad_T_39
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| _io_cpu_perf_canAcceptLoadThenLoad_T_40 | _io_cpu_perf_canAcceptLoadThenLoad_T_41
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| _io_cpu_perf_canAcceptLoadThenLoad_T_42;
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wire _io_cpu_perf_canAcceptLoadThenLoad_T_26 = s1_req_cmd == 5'h1;
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wire _io_cpu_perf_canAcceptLoadThenLoad_T_51 = s1_req_cmd == 5'h11;
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wire s1_write =
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_io_cpu_perf_canAcceptLoadThenLoad_T_26 | _io_cpu_perf_canAcceptLoadThenLoad_T_51
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| _io_cpu_perf_canAcceptLoadThenLoad_T_29 | _io_cpu_perf_canAcceptLoadThenLoad_T_31
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| _io_cpu_perf_canAcceptLoadThenLoad_T_32 | _io_cpu_perf_canAcceptLoadThenLoad_T_33
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| _io_cpu_perf_canAcceptLoadThenLoad_T_34 | _io_cpu_perf_canAcceptLoadThenLoad_T_38
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| _io_cpu_perf_canAcceptLoadThenLoad_T_39 | _io_cpu_perf_canAcceptLoadThenLoad_T_40
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| _io_cpu_perf_canAcceptLoadThenLoad_T_41 | _io_cpu_perf_canAcceptLoadThenLoad_T_42;
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reg cached_grant_wait;
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wire _io_cpu_req_ready_T_4 = ~cached_grant_wait & ~s1_nack;
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reg uncachedInFlight_0;
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reg [33:0] uncachedReqs_0_addr;
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reg [6:0] uncachedReqs_0_tag;
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reg [1:0] uncachedReqs_0_size;
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reg uncachedReqs_0_signed;
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wire _pstore_drain_opportunistic_T = io_cpu_req_bits_cmd == 5'h0;
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wire _pstore_drain_opportunistic_T_1 = io_cpu_req_bits_cmd == 5'h10;
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wire _pstore_drain_opportunistic_T_2 = io_cpu_req_bits_cmd == 5'h6;
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wire _pstore_drain_opportunistic_T_28 = io_cpu_req_bits_cmd == 5'h7;
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wire _pstore_drain_opportunistic_T_30 = io_cpu_req_bits_cmd == 5'h4;
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wire _pstore_drain_opportunistic_T_31 = io_cpu_req_bits_cmd == 5'h9;
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wire _pstore_drain_opportunistic_T_32 = io_cpu_req_bits_cmd == 5'hA;
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wire _pstore_drain_opportunistic_T_33 = io_cpu_req_bits_cmd == 5'hB;
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wire _pstore_drain_opportunistic_T_37 = io_cpu_req_bits_cmd == 5'h8;
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wire _pstore_drain_opportunistic_T_38 = io_cpu_req_bits_cmd == 5'hC;
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wire _pstore_drain_opportunistic_T_39 = io_cpu_req_bits_cmd == 5'hD;
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wire _pstore_drain_opportunistic_T_40 = io_cpu_req_bits_cmd == 5'hE;
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wire _pstore_drain_opportunistic_T_41 = io_cpu_req_bits_cmd == 5'hF;
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wire _pstore_drain_opportunistic_T_25 = io_cpu_req_bits_cmd == 5'h1;
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wire _pstore_drain_opportunistic_res_T_1 = io_cpu_req_bits_cmd == 5'h3;
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wire _dataArb_io_in_3_valid_res_T_2 =
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_pstore_drain_opportunistic_T_25 | _pstore_drain_opportunistic_res_T_1;
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wire _pstore_drain_opportunistic_T_50 = io_cpu_req_bits_cmd == 5'h11;
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wire _dataArb_io_in_3_valid_T_54 =
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~(_pstore_drain_opportunistic_T | _pstore_drain_opportunistic_T_1
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| _pstore_drain_opportunistic_T_2 | _pstore_drain_opportunistic_T_28
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| _pstore_drain_opportunistic_T_30 | _pstore_drain_opportunistic_T_31
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| _pstore_drain_opportunistic_T_32 | _pstore_drain_opportunistic_T_33
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| _pstore_drain_opportunistic_T_37 | _pstore_drain_opportunistic_T_38
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| _pstore_drain_opportunistic_T_39 | _pstore_drain_opportunistic_T_40
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| _pstore_drain_opportunistic_T_41
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| (_pstore_drain_opportunistic_T_25 | _pstore_drain_opportunistic_T_50
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| _pstore_drain_opportunistic_T_28 | _pstore_drain_opportunistic_T_30
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| _pstore_drain_opportunistic_T_31 | _pstore_drain_opportunistic_T_32
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| _pstore_drain_opportunistic_T_33 | _pstore_drain_opportunistic_T_37
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| _pstore_drain_opportunistic_T_38 | _pstore_drain_opportunistic_T_39
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| _pstore_drain_opportunistic_T_40 | _pstore_drain_opportunistic_T_41)
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& _pstore_drain_opportunistic_T_50) | ~_dataArb_io_in_3_valid_res_T_2;
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reg s1_did_read;
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wire _GEN_0 =
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~_metaArb_io_in_7_ready | ~_dataArb_io_in_3_ready
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& (_pstore_drain_opportunistic_T | _pstore_drain_opportunistic_T_1
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| _pstore_drain_opportunistic_T_2 | _pstore_drain_opportunistic_T_28
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| _pstore_drain_opportunistic_T_30 | _pstore_drain_opportunistic_T_31
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| _pstore_drain_opportunistic_T_32 | _pstore_drain_opportunistic_T_33
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| _pstore_drain_opportunistic_T_37 | _pstore_drain_opportunistic_T_38
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| _pstore_drain_opportunistic_T_39 | _pstore_drain_opportunistic_T_40
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| _pstore_drain_opportunistic_T_41);
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wire [1:0] _s1_mask_xwr_T = {s1_req_addr[0] | (|s1_req_size), ~(s1_req_addr[0])};
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wire [3:0] _s1_mask_xwr_T_1 =
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{(s1_req_addr[1] ? _s1_mask_xwr_T : 2'h0) | {2{s1_req_size[1]}},
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s1_req_addr[1] ? 2'h0 : _s1_mask_xwr_T};
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wire [3:0] s1_hazard_hi_2 =
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(s1_req_addr[2] ? _s1_mask_xwr_T_1 : 4'h0) | {4{&s1_req_size}};
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wire [3:0] s1_hazard_lo_2 = s1_req_addr[2] ? 4'h0 : _s1_mask_xwr_T_1;
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wire [7:0] s1_mask_xwr = {s1_hazard_hi_2, s1_hazard_lo_2};
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wire _GEN_1 =
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~(s1_valid_masked & _io_cpu_perf_canAcceptLoadThenLoad_T_51)
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| (&(s1_mask_xwr | ~io_cpu_s1_data_mask));
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reg s2_valid;
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wire s2_valid_no_xcpt =
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s2_valid
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& {io_cpu_s2_xcpt_ma_ld_0,
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io_cpu_s2_xcpt_ma_st_0,
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io_cpu_s2_xcpt_pf_ld_0,
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io_cpu_s2_xcpt_pf_st_0,
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io_cpu_s2_xcpt_ae_ld_0,
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io_cpu_s2_xcpt_ae_st_0} == 6'h0;
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reg s2_not_nacked_in_s1;
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wire s2_valid_masked = s2_valid_no_xcpt & s2_not_nacked_in_s1;
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reg [33:0] s2_req_addr;
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reg [6:0] s2_req_tag;
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reg [4:0] s2_req_cmd;
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reg [1:0] s2_req_size;
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reg s2_req_signed;
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reg [1:0] s2_req_dprv;
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reg s2_req_no_xcpt;
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reg s2_tlb_xcpt_pf_ld;
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reg s2_tlb_xcpt_pf_st;
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reg s2_tlb_xcpt_ae_ld;
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reg s2_tlb_xcpt_ae_st;
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reg s2_tlb_xcpt_ma_ld;
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reg s2_tlb_xcpt_ma_st;
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reg s2_pma_cacheable;
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wire _metaArb_io_in_3_bits_data_c_cat_T_48 = s2_req_cmd == 5'h6;
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wire _io_cpu_store_pending_T_3 = s2_req_cmd == 5'h7;
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wire _io_cpu_store_pending_T_5 = s2_req_cmd == 5'h4;
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wire _io_cpu_store_pending_T_6 = s2_req_cmd == 5'h9;
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wire _io_cpu_store_pending_T_7 = s2_req_cmd == 5'hA;
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wire _io_cpu_store_pending_T_8 = s2_req_cmd == 5'hB;
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wire _io_cpu_store_pending_T_12 = s2_req_cmd == 5'h8;
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wire _io_cpu_store_pending_T_13 = s2_req_cmd == 5'hC;
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wire _io_cpu_store_pending_T_14 = s2_req_cmd == 5'hD;
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wire _io_cpu_store_pending_T_15 = s2_req_cmd == 5'hE;
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wire _io_cpu_store_pending_T_16 = s2_req_cmd == 5'hF;
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wire s2_read =
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s2_req_cmd == 5'h0 | s2_req_cmd == 5'h10 | _metaArb_io_in_3_bits_data_c_cat_T_48
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| _io_cpu_store_pending_T_3 | _io_cpu_store_pending_T_5 | _io_cpu_store_pending_T_6
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| _io_cpu_store_pending_T_7 | _io_cpu_store_pending_T_8 | _io_cpu_store_pending_T_12
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| _io_cpu_store_pending_T_13 | _io_cpu_store_pending_T_14 | _io_cpu_store_pending_T_15
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| _io_cpu_store_pending_T_16;
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wire _io_cpu_store_pending_T = s2_req_cmd == 5'h1;
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wire _io_cpu_store_pending_T_1 = s2_req_cmd == 5'h11;
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wire s2_write =
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_io_cpu_store_pending_T | _io_cpu_store_pending_T_1 | _io_cpu_store_pending_T_3
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| _io_cpu_store_pending_T_5 | _io_cpu_store_pending_T_6 | _io_cpu_store_pending_T_7
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| _io_cpu_store_pending_T_8 | _io_cpu_store_pending_T_12 | _io_cpu_store_pending_T_13
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| _io_cpu_store_pending_T_14 | _io_cpu_store_pending_T_15
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| _io_cpu_store_pending_T_16;
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wire s2_readwrite = s2_read | s2_write;
|
|
reg [63:0] s2_data;
|
|
reg [1:0] s2_hit_state_state;
|
|
wire [3:0] _r_T =
|
|
{_io_cpu_store_pending_T | _io_cpu_store_pending_T_1 | _io_cpu_store_pending_T_3
|
|
| _io_cpu_store_pending_T_5 | _io_cpu_store_pending_T_6 | _io_cpu_store_pending_T_7
|
|
| _io_cpu_store_pending_T_8 | _io_cpu_store_pending_T_12
|
|
| _io_cpu_store_pending_T_13 | _io_cpu_store_pending_T_14
|
|
| _io_cpu_store_pending_T_15 | _io_cpu_store_pending_T_16,
|
|
_io_cpu_store_pending_T | _io_cpu_store_pending_T_1 | _io_cpu_store_pending_T_3
|
|
| _io_cpu_store_pending_T_5 | _io_cpu_store_pending_T_6 | _io_cpu_store_pending_T_7
|
|
| _io_cpu_store_pending_T_8 | _io_cpu_store_pending_T_12
|
|
| _io_cpu_store_pending_T_13 | _io_cpu_store_pending_T_14
|
|
| _io_cpu_store_pending_T_15 | _io_cpu_store_pending_T_16 | s2_req_cmd == 5'h3
|
|
| _metaArb_io_in_3_bits_data_c_cat_T_48,
|
|
s2_hit_state_state};
|
|
wire [1:0] _r_T_27 = {1'h0, _r_T == 4'hC};
|
|
wire s2_hit =
|
|
_r_T == 4'h3 | _r_T == 4'h2 | _r_T == 4'h1 | _r_T == 4'h7 | _r_T == 4'h6 | (&_r_T)
|
|
| _r_T == 4'hE;
|
|
wire [15:0][1:0] _GEN_2 =
|
|
{{2'h3},
|
|
{2'h3},
|
|
{2'h2},
|
|
{_r_T_27},
|
|
{_r_T_27},
|
|
{_r_T_27},
|
|
{_r_T_27},
|
|
{_r_T_27},
|
|
{2'h3},
|
|
{2'h2},
|
|
{2'h2},
|
|
{2'h1},
|
|
{2'h3},
|
|
{2'h2},
|
|
{2'h1},
|
|
{2'h0}};
|
|
wire s2_valid_hit_pre_data_ecc_and_waw =
|
|
s2_valid_masked & s2_hit & s2_readwrite;
|
|
wire s2_valid_miss = s2_valid_masked & s2_readwrite & ~s2_hit;
|
|
wire s2_valid_uncached_pending =
|
|
s2_valid_miss & ~s2_pma_cacheable & ~uncachedInFlight_0;
|
|
wire io_cpu_s2_nack_0 =
|
|
s2_valid_no_xcpt & ~(s2_valid_uncached_pending & auto_out_a_ready)
|
|
& ~(s2_valid_masked & s2_req_cmd == 5'h17) & ~s2_valid_hit_pre_data_ecc_and_waw;
|
|
wire metaArb_io_in_2_valid =
|
|
s2_valid_hit_pre_data_ecc_and_waw & s2_hit_state_state != _GEN_2[_r_T];
|
|
reg [4:0] pstore1_cmd;
|
|
reg [33:0] pstore1_addr;
|
|
reg [63:0] pstore1_data;
|
|
reg [7:0] pstore1_mask;
|
|
reg pstore1_rmw_r;
|
|
wire _pstore1_held_T_2 = s2_valid_hit_pre_data_ecc_and_waw & s2_write;
|
|
reg pstore2_valid;
|
|
wire _pstore_drain_opportunistic_res_T_2 =
|
|
_pstore_drain_opportunistic_T_25 | _pstore_drain_opportunistic_res_T_1;
|
|
wire _pstore_drain_opportunistic_T_54 =
|
|
~(_pstore_drain_opportunistic_T | _pstore_drain_opportunistic_T_1
|
|
| _pstore_drain_opportunistic_T_2 | _pstore_drain_opportunistic_T_28
|
|
| _pstore_drain_opportunistic_T_30 | _pstore_drain_opportunistic_T_31
|
|
| _pstore_drain_opportunistic_T_32 | _pstore_drain_opportunistic_T_33
|
|
| _pstore_drain_opportunistic_T_37 | _pstore_drain_opportunistic_T_38
|
|
| _pstore_drain_opportunistic_T_39 | _pstore_drain_opportunistic_T_40
|
|
| _pstore_drain_opportunistic_T_41
|
|
| (_pstore_drain_opportunistic_T_25 | _pstore_drain_opportunistic_T_50
|
|
| _pstore_drain_opportunistic_T_28 | _pstore_drain_opportunistic_T_30
|
|
| _pstore_drain_opportunistic_T_31 | _pstore_drain_opportunistic_T_32
|
|
| _pstore_drain_opportunistic_T_33 | _pstore_drain_opportunistic_T_37
|
|
| _pstore_drain_opportunistic_T_38 | _pstore_drain_opportunistic_T_39
|
|
| _pstore_drain_opportunistic_T_40 | _pstore_drain_opportunistic_T_41)
|
|
& _pstore_drain_opportunistic_T_50) | ~_pstore_drain_opportunistic_res_T_2;
|
|
reg pstore_drain_on_miss_REG;
|
|
reg pstore1_held;
|
|
wire pstore1_valid_likely = s2_valid & s2_write | pstore1_held;
|
|
wire pstore1_valid = _pstore1_held_T_2 | pstore1_held;
|
|
wire pstore_drain_structural =
|
|
pstore1_valid_likely & pstore2_valid & (s1_valid & s1_write | pstore1_rmw_r);
|
|
wire _dataArb_io_in_0_valid_T_4 =
|
|
s2_valid_hit_pre_data_ecc_and_waw & s2_write;
|
|
wire _GEN_3 =
|
|
pstore1_rmw_r | (_dataArb_io_in_0_valid_T_4 | pstore1_held) == pstore1_valid;
|
|
wire _dataArb_io_in_0_valid_T_9 =
|
|
~(io_cpu_req_valid & ~_pstore_drain_opportunistic_res_T_2) | pstore_drain_on_miss_REG;
|
|
wire dataArb_io_in_0_bits_write =
|
|
pstore_drain_structural
|
|
| ((_dataArb_io_in_0_valid_T_4 | pstore1_held) & ~pstore1_rmw_r | pstore2_valid)
|
|
& _dataArb_io_in_0_valid_T_9;
|
|
reg [33:0] pstore2_addr;
|
|
reg [7:0] pstore2_storegen_data_r;
|
|
reg [7:0] pstore2_storegen_data_r_1;
|
|
reg [7:0] pstore2_storegen_data_r_2;
|
|
reg [7:0] pstore2_storegen_data_r_3;
|
|
reg [7:0] pstore2_storegen_data_r_4;
|
|
reg [7:0] pstore2_storegen_data_r_5;
|
|
reg [7:0] pstore2_storegen_data_r_6;
|
|
reg [7:0] pstore2_storegen_data_r_7;
|
|
reg [7:0] pstore2_storegen_mask;
|
|
wire [19:0] _dataArb_io_in_0_bits_wordMask_wordMask_T =
|
|
pstore2_valid ? pstore2_addr[19:0] : pstore1_addr[19:0];
|
|
wire [63:0] dataArb_io_in_3_bits_wdata =
|
|
pstore2_valid
|
|
? {pstore2_storegen_data_r_7,
|
|
pstore2_storegen_data_r_6,
|
|
pstore2_storegen_data_r_5,
|
|
pstore2_storegen_data_r_4,
|
|
pstore2_storegen_data_r_3,
|
|
pstore2_storegen_data_r_2,
|
|
pstore2_storegen_data_r_1,
|
|
pstore2_storegen_data_r}
|
|
: pstore1_data;
|
|
wire [7:0] dataArb_io_in_1_bits_eccMask =
|
|
pstore2_valid ? pstore2_storegen_mask : pstore1_mask;
|
|
assign s1_nack =
|
|
s1_valid & s1_read
|
|
& (pstore1_valid_likely & pstore1_addr[19:3] == s1_req_addr[19:3]
|
|
& (s1_write
|
|
? (|(pstore1_mask & {s1_hazard_hi_2, s1_hazard_lo_2}))
|
|
: (|(pstore1_mask & s1_mask_xwr))) | pstore2_valid
|
|
& pstore2_addr[19:3] == s1_req_addr[19:3]
|
|
& (s1_write
|
|
? (|(pstore2_storegen_mask & {s1_hazard_hi_2, s1_hazard_lo_2}))
|
|
: (|(pstore2_storegen_mask & s1_mask_xwr)))) | io_cpu_s2_nack_0
|
|
| metaArb_io_in_2_valid;
|
|
wire [3:0] _GEN_4 = {2'h0, s2_req_size};
|
|
wire [3:0] _get_a_mask_sizeOH_T_1 = 4'h1 << _GEN_4;
|
|
wire get_a_mask_sub_sub_sub_0_1 = &s2_req_size;
|
|
wire get_a_mask_sub_sub_0_1 =
|
|
get_a_mask_sub_sub_sub_0_1 | _get_a_mask_sizeOH_T_1[2] & ~(s2_req_addr[2]);
|
|
wire get_a_mask_sub_sub_1_1 =
|
|
get_a_mask_sub_sub_sub_0_1 | _get_a_mask_sizeOH_T_1[2] & s2_req_addr[2];
|
|
wire get_a_mask_sub_0_2 = ~(s2_req_addr[2]) & ~(s2_req_addr[1]);
|
|
wire get_a_mask_sub_0_1 =
|
|
get_a_mask_sub_sub_0_1 | _get_a_mask_sizeOH_T_1[1] & get_a_mask_sub_0_2;
|
|
wire get_a_mask_sub_1_2 = ~(s2_req_addr[2]) & s2_req_addr[1];
|
|
wire get_a_mask_sub_1_1 =
|
|
get_a_mask_sub_sub_0_1 | _get_a_mask_sizeOH_T_1[1] & get_a_mask_sub_1_2;
|
|
wire get_a_mask_sub_2_2 = s2_req_addr[2] & ~(s2_req_addr[1]);
|
|
wire get_a_mask_sub_2_1 =
|
|
get_a_mask_sub_sub_1_1 | _get_a_mask_sizeOH_T_1[1] & get_a_mask_sub_2_2;
|
|
wire get_a_mask_sub_3_2 = s2_req_addr[2] & s2_req_addr[1];
|
|
wire get_a_mask_sub_3_1 =
|
|
get_a_mask_sub_sub_1_1 | _get_a_mask_sizeOH_T_1[1] & get_a_mask_sub_3_2;
|
|
wire [3:0] _put_a_mask_sizeOH_T_1 = 4'h1 << _GEN_4;
|
|
wire put_a_mask_sub_sub_0_1 =
|
|
get_a_mask_sub_sub_sub_0_1 | _put_a_mask_sizeOH_T_1[2] & ~(s2_req_addr[2]);
|
|
wire put_a_mask_sub_sub_1_1 =
|
|
get_a_mask_sub_sub_sub_0_1 | _put_a_mask_sizeOH_T_1[2] & s2_req_addr[2];
|
|
wire put_a_mask_sub_0_2 = ~(s2_req_addr[2]) & ~(s2_req_addr[1]);
|
|
wire put_a_mask_sub_0_1 =
|
|
put_a_mask_sub_sub_0_1 | _put_a_mask_sizeOH_T_1[1] & put_a_mask_sub_0_2;
|
|
wire put_a_mask_sub_1_2 = ~(s2_req_addr[2]) & s2_req_addr[1];
|
|
wire put_a_mask_sub_1_1 =
|
|
put_a_mask_sub_sub_0_1 | _put_a_mask_sizeOH_T_1[1] & put_a_mask_sub_1_2;
|
|
wire put_a_mask_sub_2_2 = s2_req_addr[2] & ~(s2_req_addr[1]);
|
|
wire put_a_mask_sub_2_1 =
|
|
put_a_mask_sub_sub_1_1 | _put_a_mask_sizeOH_T_1[1] & put_a_mask_sub_2_2;
|
|
wire put_a_mask_sub_3_2 = s2_req_addr[2] & s2_req_addr[1];
|
|
wire put_a_mask_sub_3_1 =
|
|
put_a_mask_sub_sub_1_1 | _put_a_mask_sizeOH_T_1[1] & put_a_mask_sub_3_2;
|
|
wire [3:0] _atomics_a_mask_sizeOH_T_1 = 4'h1 << _GEN_4;
|
|
wire atomics_a_mask_sub_sub_0_1 =
|
|
get_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sizeOH_T_1[2] & ~(s2_req_addr[2]);
|
|
wire atomics_a_mask_sub_sub_1_1 =
|
|
get_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sizeOH_T_1[2] & s2_req_addr[2];
|
|
wire atomics_a_mask_sub_0_2 = ~(s2_req_addr[2]) & ~(s2_req_addr[1]);
|
|
wire atomics_a_mask_sub_0_1 =
|
|
atomics_a_mask_sub_sub_0_1 | _atomics_a_mask_sizeOH_T_1[1] & atomics_a_mask_sub_0_2;
|
|
wire atomics_a_mask_sub_1_2 = ~(s2_req_addr[2]) & s2_req_addr[1];
|
|
wire atomics_a_mask_sub_1_1 =
|
|
atomics_a_mask_sub_sub_0_1 | _atomics_a_mask_sizeOH_T_1[1] & atomics_a_mask_sub_1_2;
|
|
wire atomics_a_mask_sub_2_2 = s2_req_addr[2] & ~(s2_req_addr[1]);
|
|
wire atomics_a_mask_sub_2_1 =
|
|
atomics_a_mask_sub_sub_1_1 | _atomics_a_mask_sizeOH_T_1[1] & atomics_a_mask_sub_2_2;
|
|
wire atomics_a_mask_sub_3_2 = s2_req_addr[2] & s2_req_addr[1];
|
|
wire atomics_a_mask_sub_3_1 =
|
|
atomics_a_mask_sub_sub_1_1 | _atomics_a_mask_sizeOH_T_1[1] & atomics_a_mask_sub_3_2;
|
|
wire [3:0] _atomics_a_mask_sizeOH_T_4 = 4'h1 << _GEN_4;
|
|
wire atomics_a_mask_sub_sub_0_1_1 =
|
|
get_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sizeOH_T_4[2] & ~(s2_req_addr[2]);
|
|
wire atomics_a_mask_sub_sub_1_1_1 =
|
|
get_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sizeOH_T_4[2] & s2_req_addr[2];
|
|
wire atomics_a_mask_sub_0_2_1 = ~(s2_req_addr[2]) & ~(s2_req_addr[1]);
|
|
wire atomics_a_mask_sub_0_1_1 =
|
|
atomics_a_mask_sub_sub_0_1_1 | _atomics_a_mask_sizeOH_T_4[1]
|
|
& atomics_a_mask_sub_0_2_1;
|
|
wire atomics_a_mask_sub_1_2_1 = ~(s2_req_addr[2]) & s2_req_addr[1];
|
|
wire atomics_a_mask_sub_1_1_1 =
|
|
atomics_a_mask_sub_sub_0_1_1 | _atomics_a_mask_sizeOH_T_4[1]
|
|
& atomics_a_mask_sub_1_2_1;
|
|
wire atomics_a_mask_sub_2_2_1 = s2_req_addr[2] & ~(s2_req_addr[1]);
|
|
wire atomics_a_mask_sub_2_1_1 =
|
|
atomics_a_mask_sub_sub_1_1_1 | _atomics_a_mask_sizeOH_T_4[1]
|
|
& atomics_a_mask_sub_2_2_1;
|
|
wire atomics_a_mask_sub_3_2_1 = s2_req_addr[2] & s2_req_addr[1];
|
|
wire atomics_a_mask_sub_3_1_1 =
|
|
atomics_a_mask_sub_sub_1_1_1 | _atomics_a_mask_sizeOH_T_4[1]
|
|
& atomics_a_mask_sub_3_2_1;
|
|
wire [3:0] _atomics_a_mask_sizeOH_T_7 = 4'h1 << _GEN_4;
|
|
wire atomics_a_mask_sub_sub_0_1_2 =
|
|
get_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sizeOH_T_7[2] & ~(s2_req_addr[2]);
|
|
wire atomics_a_mask_sub_sub_1_1_2 =
|
|
get_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sizeOH_T_7[2] & s2_req_addr[2];
|
|
wire atomics_a_mask_sub_0_2_2 = ~(s2_req_addr[2]) & ~(s2_req_addr[1]);
|
|
wire atomics_a_mask_sub_0_1_2 =
|
|
atomics_a_mask_sub_sub_0_1_2 | _atomics_a_mask_sizeOH_T_7[1]
|
|
& atomics_a_mask_sub_0_2_2;
|
|
wire atomics_a_mask_sub_1_2_2 = ~(s2_req_addr[2]) & s2_req_addr[1];
|
|
wire atomics_a_mask_sub_1_1_2 =
|
|
atomics_a_mask_sub_sub_0_1_2 | _atomics_a_mask_sizeOH_T_7[1]
|
|
& atomics_a_mask_sub_1_2_2;
|
|
wire atomics_a_mask_sub_2_2_2 = s2_req_addr[2] & ~(s2_req_addr[1]);
|
|
wire atomics_a_mask_sub_2_1_2 =
|
|
atomics_a_mask_sub_sub_1_1_2 | _atomics_a_mask_sizeOH_T_7[1]
|
|
& atomics_a_mask_sub_2_2_2;
|
|
wire atomics_a_mask_sub_3_2_2 = s2_req_addr[2] & s2_req_addr[1];
|
|
wire atomics_a_mask_sub_3_1_2 =
|
|
atomics_a_mask_sub_sub_1_1_2 | _atomics_a_mask_sizeOH_T_7[1]
|
|
& atomics_a_mask_sub_3_2_2;
|
|
wire [3:0] _atomics_a_mask_sizeOH_T_10 = 4'h1 << _GEN_4;
|
|
wire atomics_a_mask_sub_sub_0_1_3 =
|
|
get_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sizeOH_T_10[2] & ~(s2_req_addr[2]);
|
|
wire atomics_a_mask_sub_sub_1_1_3 =
|
|
get_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sizeOH_T_10[2] & s2_req_addr[2];
|
|
wire atomics_a_mask_sub_0_2_3 = ~(s2_req_addr[2]) & ~(s2_req_addr[1]);
|
|
wire atomics_a_mask_sub_0_1_3 =
|
|
atomics_a_mask_sub_sub_0_1_3 | _atomics_a_mask_sizeOH_T_10[1]
|
|
& atomics_a_mask_sub_0_2_3;
|
|
wire atomics_a_mask_sub_1_2_3 = ~(s2_req_addr[2]) & s2_req_addr[1];
|
|
wire atomics_a_mask_sub_1_1_3 =
|
|
atomics_a_mask_sub_sub_0_1_3 | _atomics_a_mask_sizeOH_T_10[1]
|
|
& atomics_a_mask_sub_1_2_3;
|
|
wire atomics_a_mask_sub_2_2_3 = s2_req_addr[2] & ~(s2_req_addr[1]);
|
|
wire atomics_a_mask_sub_2_1_3 =
|
|
atomics_a_mask_sub_sub_1_1_3 | _atomics_a_mask_sizeOH_T_10[1]
|
|
& atomics_a_mask_sub_2_2_3;
|
|
wire atomics_a_mask_sub_3_2_3 = s2_req_addr[2] & s2_req_addr[1];
|
|
wire atomics_a_mask_sub_3_1_3 =
|
|
atomics_a_mask_sub_sub_1_1_3 | _atomics_a_mask_sizeOH_T_10[1]
|
|
& atomics_a_mask_sub_3_2_3;
|
|
wire [3:0] _atomics_a_mask_sizeOH_T_13 = 4'h1 << _GEN_4;
|
|
wire atomics_a_mask_sub_sub_0_1_4 =
|
|
get_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sizeOH_T_13[2] & ~(s2_req_addr[2]);
|
|
wire atomics_a_mask_sub_sub_1_1_4 =
|
|
get_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sizeOH_T_13[2] & s2_req_addr[2];
|
|
wire atomics_a_mask_sub_0_2_4 = ~(s2_req_addr[2]) & ~(s2_req_addr[1]);
|
|
wire atomics_a_mask_sub_0_1_4 =
|
|
atomics_a_mask_sub_sub_0_1_4 | _atomics_a_mask_sizeOH_T_13[1]
|
|
& atomics_a_mask_sub_0_2_4;
|
|
wire atomics_a_mask_sub_1_2_4 = ~(s2_req_addr[2]) & s2_req_addr[1];
|
|
wire atomics_a_mask_sub_1_1_4 =
|
|
atomics_a_mask_sub_sub_0_1_4 | _atomics_a_mask_sizeOH_T_13[1]
|
|
& atomics_a_mask_sub_1_2_4;
|
|
wire atomics_a_mask_sub_2_2_4 = s2_req_addr[2] & ~(s2_req_addr[1]);
|
|
wire atomics_a_mask_sub_2_1_4 =
|
|
atomics_a_mask_sub_sub_1_1_4 | _atomics_a_mask_sizeOH_T_13[1]
|
|
& atomics_a_mask_sub_2_2_4;
|
|
wire atomics_a_mask_sub_3_2_4 = s2_req_addr[2] & s2_req_addr[1];
|
|
wire atomics_a_mask_sub_3_1_4 =
|
|
atomics_a_mask_sub_sub_1_1_4 | _atomics_a_mask_sizeOH_T_13[1]
|
|
& atomics_a_mask_sub_3_2_4;
|
|
wire [3:0] _atomics_a_mask_sizeOH_T_16 = 4'h1 << _GEN_4;
|
|
wire atomics_a_mask_sub_sub_0_1_5 =
|
|
get_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sizeOH_T_16[2] & ~(s2_req_addr[2]);
|
|
wire atomics_a_mask_sub_sub_1_1_5 =
|
|
get_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sizeOH_T_16[2] & s2_req_addr[2];
|
|
wire atomics_a_mask_sub_0_2_5 = ~(s2_req_addr[2]) & ~(s2_req_addr[1]);
|
|
wire atomics_a_mask_sub_0_1_5 =
|
|
atomics_a_mask_sub_sub_0_1_5 | _atomics_a_mask_sizeOH_T_16[1]
|
|
& atomics_a_mask_sub_0_2_5;
|
|
wire atomics_a_mask_sub_1_2_5 = ~(s2_req_addr[2]) & s2_req_addr[1];
|
|
wire atomics_a_mask_sub_1_1_5 =
|
|
atomics_a_mask_sub_sub_0_1_5 | _atomics_a_mask_sizeOH_T_16[1]
|
|
& atomics_a_mask_sub_1_2_5;
|
|
wire atomics_a_mask_sub_2_2_5 = s2_req_addr[2] & ~(s2_req_addr[1]);
|
|
wire atomics_a_mask_sub_2_1_5 =
|
|
atomics_a_mask_sub_sub_1_1_5 | _atomics_a_mask_sizeOH_T_16[1]
|
|
& atomics_a_mask_sub_2_2_5;
|
|
wire atomics_a_mask_sub_3_2_5 = s2_req_addr[2] & s2_req_addr[1];
|
|
wire atomics_a_mask_sub_3_1_5 =
|
|
atomics_a_mask_sub_sub_1_1_5 | _atomics_a_mask_sizeOH_T_16[1]
|
|
& atomics_a_mask_sub_3_2_5;
|
|
wire [3:0] _atomics_a_mask_sizeOH_T_19 = 4'h1 << _GEN_4;
|
|
wire atomics_a_mask_sub_sub_0_1_6 =
|
|
get_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sizeOH_T_19[2] & ~(s2_req_addr[2]);
|
|
wire atomics_a_mask_sub_sub_1_1_6 =
|
|
get_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sizeOH_T_19[2] & s2_req_addr[2];
|
|
wire atomics_a_mask_sub_0_2_6 = ~(s2_req_addr[2]) & ~(s2_req_addr[1]);
|
|
wire atomics_a_mask_sub_0_1_6 =
|
|
atomics_a_mask_sub_sub_0_1_6 | _atomics_a_mask_sizeOH_T_19[1]
|
|
& atomics_a_mask_sub_0_2_6;
|
|
wire atomics_a_mask_sub_1_2_6 = ~(s2_req_addr[2]) & s2_req_addr[1];
|
|
wire atomics_a_mask_sub_1_1_6 =
|
|
atomics_a_mask_sub_sub_0_1_6 | _atomics_a_mask_sizeOH_T_19[1]
|
|
& atomics_a_mask_sub_1_2_6;
|
|
wire atomics_a_mask_sub_2_2_6 = s2_req_addr[2] & ~(s2_req_addr[1]);
|
|
wire atomics_a_mask_sub_2_1_6 =
|
|
atomics_a_mask_sub_sub_1_1_6 | _atomics_a_mask_sizeOH_T_19[1]
|
|
& atomics_a_mask_sub_2_2_6;
|
|
wire atomics_a_mask_sub_3_2_6 = s2_req_addr[2] & s2_req_addr[1];
|
|
wire atomics_a_mask_sub_3_1_6 =
|
|
atomics_a_mask_sub_sub_1_1_6 | _atomics_a_mask_sizeOH_T_19[1]
|
|
& atomics_a_mask_sub_3_2_6;
|
|
wire [3:0] _atomics_a_mask_sizeOH_T_22 = 4'h1 << _GEN_4;
|
|
wire atomics_a_mask_sub_sub_0_1_7 =
|
|
get_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sizeOH_T_22[2] & ~(s2_req_addr[2]);
|
|
wire atomics_a_mask_sub_sub_1_1_7 =
|
|
get_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sizeOH_T_22[2] & s2_req_addr[2];
|
|
wire atomics_a_mask_sub_0_2_7 = ~(s2_req_addr[2]) & ~(s2_req_addr[1]);
|
|
wire atomics_a_mask_sub_0_1_7 =
|
|
atomics_a_mask_sub_sub_0_1_7 | _atomics_a_mask_sizeOH_T_22[1]
|
|
& atomics_a_mask_sub_0_2_7;
|
|
wire atomics_a_mask_sub_1_2_7 = ~(s2_req_addr[2]) & s2_req_addr[1];
|
|
wire atomics_a_mask_sub_1_1_7 =
|
|
atomics_a_mask_sub_sub_0_1_7 | _atomics_a_mask_sizeOH_T_22[1]
|
|
& atomics_a_mask_sub_1_2_7;
|
|
wire atomics_a_mask_sub_2_2_7 = s2_req_addr[2] & ~(s2_req_addr[1]);
|
|
wire atomics_a_mask_sub_2_1_7 =
|
|
atomics_a_mask_sub_sub_1_1_7 | _atomics_a_mask_sizeOH_T_22[1]
|
|
& atomics_a_mask_sub_2_2_7;
|
|
wire atomics_a_mask_sub_3_2_7 = s2_req_addr[2] & s2_req_addr[1];
|
|
wire atomics_a_mask_sub_3_1_7 =
|
|
atomics_a_mask_sub_sub_1_1_7 | _atomics_a_mask_sizeOH_T_22[1]
|
|
& atomics_a_mask_sub_3_2_7;
|
|
wire [3:0] _atomics_a_mask_sizeOH_T_25 = 4'h1 << _GEN_4;
|
|
wire atomics_a_mask_sub_sub_0_1_8 =
|
|
get_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sizeOH_T_25[2] & ~(s2_req_addr[2]);
|
|
wire atomics_a_mask_sub_sub_1_1_8 =
|
|
get_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sizeOH_T_25[2] & s2_req_addr[2];
|
|
wire atomics_a_mask_sub_0_2_8 = ~(s2_req_addr[2]) & ~(s2_req_addr[1]);
|
|
wire atomics_a_mask_sub_0_1_8 =
|
|
atomics_a_mask_sub_sub_0_1_8 | _atomics_a_mask_sizeOH_T_25[1]
|
|
& atomics_a_mask_sub_0_2_8;
|
|
wire atomics_a_mask_sub_1_2_8 = ~(s2_req_addr[2]) & s2_req_addr[1];
|
|
wire atomics_a_mask_sub_1_1_8 =
|
|
atomics_a_mask_sub_sub_0_1_8 | _atomics_a_mask_sizeOH_T_25[1]
|
|
& atomics_a_mask_sub_1_2_8;
|
|
wire atomics_a_mask_sub_2_2_8 = s2_req_addr[2] & ~(s2_req_addr[1]);
|
|
wire atomics_a_mask_sub_2_1_8 =
|
|
atomics_a_mask_sub_sub_1_1_8 | _atomics_a_mask_sizeOH_T_25[1]
|
|
& atomics_a_mask_sub_2_2_8;
|
|
wire atomics_a_mask_sub_3_2_8 = s2_req_addr[2] & s2_req_addr[1];
|
|
wire atomics_a_mask_sub_3_1_8 =
|
|
atomics_a_mask_sub_sub_1_1_8 | _atomics_a_mask_sizeOH_T_25[1]
|
|
& atomics_a_mask_sub_3_2_8;
|
|
wire _GEN_5 =
|
|
_io_cpu_store_pending_T_8 | _io_cpu_store_pending_T_7 | _io_cpu_store_pending_T_6
|
|
| _io_cpu_store_pending_T_5;
|
|
wire [7:0] atomics_mask =
|
|
_io_cpu_store_pending_T_16
|
|
? {atomics_a_mask_sub_3_1_8 | atomics_a_mask_sub_3_2_8 & s2_req_addr[0],
|
|
atomics_a_mask_sub_3_1_8 | atomics_a_mask_sub_3_2_8 & ~(s2_req_addr[0]),
|
|
atomics_a_mask_sub_2_1_8 | atomics_a_mask_sub_2_2_8 & s2_req_addr[0],
|
|
atomics_a_mask_sub_2_1_8 | atomics_a_mask_sub_2_2_8 & ~(s2_req_addr[0]),
|
|
atomics_a_mask_sub_1_1_8 | atomics_a_mask_sub_1_2_8 & s2_req_addr[0],
|
|
atomics_a_mask_sub_1_1_8 | atomics_a_mask_sub_1_2_8 & ~(s2_req_addr[0]),
|
|
atomics_a_mask_sub_0_1_8 | atomics_a_mask_sub_0_2_8 & s2_req_addr[0],
|
|
atomics_a_mask_sub_0_1_8 | atomics_a_mask_sub_0_2_8 & ~(s2_req_addr[0])}
|
|
: _io_cpu_store_pending_T_15
|
|
? {atomics_a_mask_sub_3_1_7 | atomics_a_mask_sub_3_2_7 & s2_req_addr[0],
|
|
atomics_a_mask_sub_3_1_7 | atomics_a_mask_sub_3_2_7 & ~(s2_req_addr[0]),
|
|
atomics_a_mask_sub_2_1_7 | atomics_a_mask_sub_2_2_7 & s2_req_addr[0],
|
|
atomics_a_mask_sub_2_1_7 | atomics_a_mask_sub_2_2_7 & ~(s2_req_addr[0]),
|
|
atomics_a_mask_sub_1_1_7 | atomics_a_mask_sub_1_2_7 & s2_req_addr[0],
|
|
atomics_a_mask_sub_1_1_7 | atomics_a_mask_sub_1_2_7 & ~(s2_req_addr[0]),
|
|
atomics_a_mask_sub_0_1_7 | atomics_a_mask_sub_0_2_7 & s2_req_addr[0],
|
|
atomics_a_mask_sub_0_1_7 | atomics_a_mask_sub_0_2_7 & ~(s2_req_addr[0])}
|
|
: _io_cpu_store_pending_T_14
|
|
? {atomics_a_mask_sub_3_1_6 | atomics_a_mask_sub_3_2_6 & s2_req_addr[0],
|
|
atomics_a_mask_sub_3_1_6 | atomics_a_mask_sub_3_2_6 & ~(s2_req_addr[0]),
|
|
atomics_a_mask_sub_2_1_6 | atomics_a_mask_sub_2_2_6 & s2_req_addr[0],
|
|
atomics_a_mask_sub_2_1_6 | atomics_a_mask_sub_2_2_6 & ~(s2_req_addr[0]),
|
|
atomics_a_mask_sub_1_1_6 | atomics_a_mask_sub_1_2_6 & s2_req_addr[0],
|
|
atomics_a_mask_sub_1_1_6 | atomics_a_mask_sub_1_2_6 & ~(s2_req_addr[0]),
|
|
atomics_a_mask_sub_0_1_6 | atomics_a_mask_sub_0_2_6 & s2_req_addr[0],
|
|
atomics_a_mask_sub_0_1_6 | atomics_a_mask_sub_0_2_6 & ~(s2_req_addr[0])}
|
|
: _io_cpu_store_pending_T_13
|
|
? {atomics_a_mask_sub_3_1_5 | atomics_a_mask_sub_3_2_5 & s2_req_addr[0],
|
|
atomics_a_mask_sub_3_1_5 | atomics_a_mask_sub_3_2_5
|
|
& ~(s2_req_addr[0]),
|
|
atomics_a_mask_sub_2_1_5 | atomics_a_mask_sub_2_2_5 & s2_req_addr[0],
|
|
atomics_a_mask_sub_2_1_5 | atomics_a_mask_sub_2_2_5
|
|
& ~(s2_req_addr[0]),
|
|
atomics_a_mask_sub_1_1_5 | atomics_a_mask_sub_1_2_5 & s2_req_addr[0],
|
|
atomics_a_mask_sub_1_1_5 | atomics_a_mask_sub_1_2_5
|
|
& ~(s2_req_addr[0]),
|
|
atomics_a_mask_sub_0_1_5 | atomics_a_mask_sub_0_2_5 & s2_req_addr[0],
|
|
atomics_a_mask_sub_0_1_5 | atomics_a_mask_sub_0_2_5
|
|
& ~(s2_req_addr[0])}
|
|
: _io_cpu_store_pending_T_12
|
|
? {atomics_a_mask_sub_3_1_4 | atomics_a_mask_sub_3_2_4
|
|
& s2_req_addr[0],
|
|
atomics_a_mask_sub_3_1_4 | atomics_a_mask_sub_3_2_4
|
|
& ~(s2_req_addr[0]),
|
|
atomics_a_mask_sub_2_1_4 | atomics_a_mask_sub_2_2_4
|
|
& s2_req_addr[0],
|
|
atomics_a_mask_sub_2_1_4 | atomics_a_mask_sub_2_2_4
|
|
& ~(s2_req_addr[0]),
|
|
atomics_a_mask_sub_1_1_4 | atomics_a_mask_sub_1_2_4
|
|
& s2_req_addr[0],
|
|
atomics_a_mask_sub_1_1_4 | atomics_a_mask_sub_1_2_4
|
|
& ~(s2_req_addr[0]),
|
|
atomics_a_mask_sub_0_1_4 | atomics_a_mask_sub_0_2_4
|
|
& s2_req_addr[0],
|
|
atomics_a_mask_sub_0_1_4 | atomics_a_mask_sub_0_2_4
|
|
& ~(s2_req_addr[0])}
|
|
: _io_cpu_store_pending_T_8
|
|
? {atomics_a_mask_sub_3_1_3 | atomics_a_mask_sub_3_2_3
|
|
& s2_req_addr[0],
|
|
atomics_a_mask_sub_3_1_3 | atomics_a_mask_sub_3_2_3
|
|
& ~(s2_req_addr[0]),
|
|
atomics_a_mask_sub_2_1_3 | atomics_a_mask_sub_2_2_3
|
|
& s2_req_addr[0],
|
|
atomics_a_mask_sub_2_1_3 | atomics_a_mask_sub_2_2_3
|
|
& ~(s2_req_addr[0]),
|
|
atomics_a_mask_sub_1_1_3 | atomics_a_mask_sub_1_2_3
|
|
& s2_req_addr[0],
|
|
atomics_a_mask_sub_1_1_3 | atomics_a_mask_sub_1_2_3
|
|
& ~(s2_req_addr[0]),
|
|
atomics_a_mask_sub_0_1_3 | atomics_a_mask_sub_0_2_3
|
|
& s2_req_addr[0],
|
|
atomics_a_mask_sub_0_1_3 | atomics_a_mask_sub_0_2_3
|
|
& ~(s2_req_addr[0])}
|
|
: _io_cpu_store_pending_T_7
|
|
? {atomics_a_mask_sub_3_1_2 | atomics_a_mask_sub_3_2_2
|
|
& s2_req_addr[0],
|
|
atomics_a_mask_sub_3_1_2 | atomics_a_mask_sub_3_2_2
|
|
& ~(s2_req_addr[0]),
|
|
atomics_a_mask_sub_2_1_2 | atomics_a_mask_sub_2_2_2
|
|
& s2_req_addr[0],
|
|
atomics_a_mask_sub_2_1_2 | atomics_a_mask_sub_2_2_2
|
|
& ~(s2_req_addr[0]),
|
|
atomics_a_mask_sub_1_1_2 | atomics_a_mask_sub_1_2_2
|
|
& s2_req_addr[0],
|
|
atomics_a_mask_sub_1_1_2 | atomics_a_mask_sub_1_2_2
|
|
& ~(s2_req_addr[0]),
|
|
atomics_a_mask_sub_0_1_2 | atomics_a_mask_sub_0_2_2
|
|
& s2_req_addr[0],
|
|
atomics_a_mask_sub_0_1_2 | atomics_a_mask_sub_0_2_2
|
|
& ~(s2_req_addr[0])}
|
|
: _io_cpu_store_pending_T_6
|
|
? {atomics_a_mask_sub_3_1_1 | atomics_a_mask_sub_3_2_1
|
|
& s2_req_addr[0],
|
|
atomics_a_mask_sub_3_1_1 | atomics_a_mask_sub_3_2_1
|
|
& ~(s2_req_addr[0]),
|
|
atomics_a_mask_sub_2_1_1 | atomics_a_mask_sub_2_2_1
|
|
& s2_req_addr[0],
|
|
atomics_a_mask_sub_2_1_1 | atomics_a_mask_sub_2_2_1
|
|
& ~(s2_req_addr[0]),
|
|
atomics_a_mask_sub_1_1_1 | atomics_a_mask_sub_1_2_1
|
|
& s2_req_addr[0],
|
|
atomics_a_mask_sub_1_1_1 | atomics_a_mask_sub_1_2_1
|
|
& ~(s2_req_addr[0]),
|
|
atomics_a_mask_sub_0_1_1 | atomics_a_mask_sub_0_2_1
|
|
& s2_req_addr[0],
|
|
atomics_a_mask_sub_0_1_1 | atomics_a_mask_sub_0_2_1
|
|
& ~(s2_req_addr[0])}
|
|
: _io_cpu_store_pending_T_5
|
|
? {atomics_a_mask_sub_3_1 | atomics_a_mask_sub_3_2
|
|
& s2_req_addr[0],
|
|
atomics_a_mask_sub_3_1 | atomics_a_mask_sub_3_2
|
|
& ~(s2_req_addr[0]),
|
|
atomics_a_mask_sub_2_1 | atomics_a_mask_sub_2_2
|
|
& s2_req_addr[0],
|
|
atomics_a_mask_sub_2_1 | atomics_a_mask_sub_2_2
|
|
& ~(s2_req_addr[0]),
|
|
atomics_a_mask_sub_1_1 | atomics_a_mask_sub_1_2
|
|
& s2_req_addr[0],
|
|
atomics_a_mask_sub_1_1 | atomics_a_mask_sub_1_2
|
|
& ~(s2_req_addr[0]),
|
|
atomics_a_mask_sub_0_1 | atomics_a_mask_sub_0_2
|
|
& s2_req_addr[0],
|
|
atomics_a_mask_sub_0_1 | atomics_a_mask_sub_0_2
|
|
& ~(s2_req_addr[0])}
|
|
: 8'h0;
|
|
wire tl_out_a_valid =
|
|
s2_valid_uncached_pending | s2_valid_miss & s2_pma_cacheable & ~uncachedInFlight_0
|
|
& ((|s2_hit_state_state) ? s2_hit_state_state : 2'h0) != 2'h3;
|
|
wire _GEN_6 =
|
|
_io_cpu_store_pending_T_1 | ~s2_read | _io_cpu_store_pending_T_16
|
|
| _io_cpu_store_pending_T_15 | _io_cpu_store_pending_T_14 | _io_cpu_store_pending_T_13
|
|
| _io_cpu_store_pending_T_12 | _GEN_5;
|
|
wire _GEN_7 = s2_pma_cacheable | ~(~s2_write | _GEN_6);
|
|
wire _io_errors_bus_valid_T = ~_GEN & auto_out_d_valid;
|
|
wire [26:0] _r_beats1_decode_T = 27'hFFF << auto_out_d_bits_size;
|
|
wire [8:0] r_beats1 =
|
|
auto_out_d_bits_opcode[0] ? ~(_r_beats1_decode_T[11:3]) : 9'h0;
|
|
reg [8:0] r_counter;
|
|
wire d_last = r_counter == 9'h1 | r_beats1 == 9'h0;
|
|
wire _GEN_8 =
|
|
~auto_out_d_valid | auto_out_d_bits_opcode == 3'h1 | auto_out_d_bits_opcode == 3'h0
|
|
| auto_out_d_bits_opcode == 3'h2;
|
|
wire grantIsUncachedData =
|
|
&{auto_out_d_bits_opcode[0], ~(auto_out_d_bits_opcode[1])};
|
|
wire _GEN_9 = _io_errors_bus_valid_T & d_last & ~reset;
|
|
wire _GEN_10 = _io_errors_bus_valid_T & grantIsUncachedData;
|
|
reg blockUncachedGrant;
|
|
assign _GEN = grantIsUncachedData & (blockUncachedGrant | s1_valid);
|
|
wire io_cpu_req_ready_0 =
|
|
_GEN
|
|
? ~(auto_out_d_valid | _GEN_0) & _io_cpu_req_ready_T_4
|
|
: ~_GEN_0 & _io_cpu_req_ready_T_4;
|
|
wire _GEN_11 = _GEN & auto_out_d_valid;
|
|
reg io_cpu_s2_xcpt_REG;
|
|
assign io_cpu_s2_xcpt_pf_ld_0 = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_ld;
|
|
assign io_cpu_s2_xcpt_pf_st_0 = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_st;
|
|
assign io_cpu_s2_xcpt_ae_ld_0 = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_ld;
|
|
assign io_cpu_s2_xcpt_ae_st_0 = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_st;
|
|
assign io_cpu_s2_xcpt_ma_ld_0 = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ma_ld;
|
|
assign io_cpu_s2_xcpt_ma_st_0 = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ma_st;
|
|
wire _GEN_12 =
|
|
s2_valid_masked & (_metaArb_io_in_3_bits_data_c_cat_T_48 | _io_cpu_store_pending_T_3);
|
|
reg doUncachedResp;
|
|
wire io_cpu_replay_next_0 = _io_errors_bus_valid_T & grantIsUncachedData;
|
|
wire _GEN_13 = doUncachedResp & ~reset;
|
|
`ifndef SYNTHESIS
|
|
always @(posedge clock) begin
|
|
if ((`PRINTF_COND_) & ~reset & ~_dataArb_io_in_3_valid_T_54)
|
|
$fwrite(32'h80000002,
|
|
"Assertion failed\n at DCache.scala:1184 assert(!needsRead(req) || res)\n");
|
|
if ((`PRINTF_COND_) & ~reset & ~_GEN_1)
|
|
$fwrite(32'h80000002,
|
|
"Assertion failed\n at DCache.scala:327 assert(!(s1_valid_masked && s1_req.cmd === M_PWR) || (s1_mask_xwr | ~io.cpu.s1_data.mask).andR)\n");
|
|
if ((`PRINTF_COND_) & ~reset & ~_pstore_drain_opportunistic_T_54)
|
|
$fwrite(32'h80000002,
|
|
"Assertion failed\n at DCache.scala:1184 assert(!needsRead(req) || res)\n");
|
|
if ((`PRINTF_COND_) & ~reset & ~_GEN_3)
|
|
$fwrite(32'h80000002,
|
|
"Assertion failed\n at DCache.scala:508 assert(pstore1_rmw || pstore1_valid_not_rmw(io.cpu.s2_kill) === pstore1_valid)\n");
|
|
if ((`PRINTF_COND_) & ~reset & ~_GEN_8)
|
|
$fwrite(32'h80000002,
|
|
"Assertion failed\n at DCache.scala:652 assert(!tl_out.d.valid || whole_opc.isOneOf(uncachedGrantOpcodes))\n");
|
|
if ((`PRINTF_COND_) & _GEN_9 & ~uncachedInFlight_0)
|
|
$fwrite(32'h80000002,
|
|
"Assertion failed: An AccessAck was unexpected by the dcache.\n at DCache.scala:685 assert(f, \"An AccessAck was unexpected by the dcache.\") // TODO must handle Ack coming back on same cycle!\n");
|
|
if ((`PRINTF_COND_) & ~reset & _GEN_12)
|
|
$fwrite(32'h80000002,
|
|
"Assertion failed\n at DCache.scala:934 assert(!(s2_valid_masked && s2_req.cmd.isOneOf(M_XLR, M_XSC)))\n");
|
|
if ((`PRINTF_COND_) & _GEN_13 & s2_valid_hit_pre_data_ecc_and_waw)
|
|
$fwrite(32'h80000002,
|
|
"Assertion failed\n at DCache.scala:950 assert(!s2_valid_hit)\n");
|
|
end // always @(posedge)
|
|
`endif // not def SYNTHESIS
|
|
wire [31:0] io_cpu_resp_bits_data_zeroed =
|
|
s2_req_addr[2] ? s2_data[63:32] : s2_data[31:0];
|
|
wire _io_cpu_resp_bits_data_word_bypass_T_1 = s2_req_size == 2'h2;
|
|
wire [15:0] io_cpu_resp_bits_data_zeroed_1 =
|
|
s2_req_addr[1]
|
|
? io_cpu_resp_bits_data_zeroed[31:16]
|
|
: io_cpu_resp_bits_data_zeroed[15:0];
|
|
wire [7:0] io_cpu_resp_bits_data_zeroed_2 =
|
|
s2_req_addr[0]
|
|
? io_cpu_resp_bits_data_zeroed_1[15:8]
|
|
: io_cpu_resp_bits_data_zeroed_1[7:0];
|
|
wire [31:0] io_cpu_resp_bits_data_word_bypass_zeroed =
|
|
s2_req_addr[2] ? s2_data[63:32] : s2_data[31:0];
|
|
wire [63:0] pstore1_storegen_data_mask =
|
|
{{8{pstore1_mask[7]}},
|
|
{8{pstore1_mask[6]}},
|
|
{8{pstore1_mask[5]}},
|
|
{8{pstore1_mask[4]}},
|
|
{8{pstore1_mask[3]}},
|
|
{8{pstore1_mask[2]}},
|
|
{8{pstore1_mask[1]}},
|
|
{8{pstore1_mask[0]}}};
|
|
wire [63:0] pstore1_storegen_data =
|
|
_amoalus_0_io_out_unmasked & pstore1_storegen_data_mask | s2_data
|
|
& ~pstore1_storegen_data_mask;
|
|
always @(posedge clock) begin
|
|
automatic logic s1_valid_not_nacked;
|
|
automatic logic advance_pstore1;
|
|
automatic logic _io_cpu_perf_acquire_T;
|
|
automatic logic _GEN_14;
|
|
s1_valid_not_nacked = s1_valid & ~s1_nack;
|
|
advance_pstore1 = pstore1_valid & pstore2_valid == dataArb_io_in_0_bits_write;
|
|
_io_cpu_perf_acquire_T = auto_out_a_ready & tl_out_a_valid;
|
|
_GEN_14 = _io_cpu_perf_acquire_T & ~s2_pma_cacheable;
|
|
if (~reset) begin
|
|
end
|
|
if (reset) begin
|
|
s1_valid <= 1'h0;
|
|
cached_grant_wait <= 1'h0;
|
|
uncachedInFlight_0 <= 1'h0;
|
|
s2_valid <= 1'h0;
|
|
pstore2_valid <= 1'h0;
|
|
pstore1_held <= 1'h0;
|
|
r_counter <= 9'h0;
|
|
end
|
|
else begin
|
|
s1_valid <= io_cpu_req_ready_0 & io_cpu_req_valid;
|
|
cached_grant_wait <= _io_cpu_perf_acquire_T & s2_pma_cacheable | cached_grant_wait;
|
|
uncachedInFlight_0 <=
|
|
(~_io_errors_bus_valid_T | ~d_last) & (_GEN_14 | uncachedInFlight_0);
|
|
s2_valid <=
|
|
s1_valid_masked
|
|
& ~(s1_req_cmd == 5'h14 | s1_req_cmd == 5'h15 | s1_req_cmd == 5'h16);
|
|
pstore2_valid <= pstore2_valid & ~dataArb_io_in_0_bits_write | advance_pstore1;
|
|
pstore1_held <=
|
|
(_pstore1_held_T_2 | pstore1_held) & pstore2_valid & ~dataArb_io_in_0_bits_write;
|
|
if (_io_errors_bus_valid_T)
|
|
r_counter <= (|r_counter) ? r_counter - 9'h1 : r_beats1;
|
|
end
|
|
if (_metaArb_io_out_valid & ~_metaArb_io_out_bits_write) begin
|
|
automatic logic [33:0] s0_req_addr =
|
|
{_metaArb_io_out_bits_addr[33:6], io_cpu_req_bits_addr[5:0]};
|
|
s1_req_addr <= s0_req_addr;
|
|
s1_req_tag <= io_cpu_req_bits_tag;
|
|
s1_req_cmd <= io_cpu_req_bits_cmd;
|
|
s1_req_size <= io_cpu_req_bits_size;
|
|
s1_req_signed <= io_cpu_req_bits_signed;
|
|
s1_req_dprv <= io_cpu_req_bits_dprv;
|
|
s1_req_no_xcpt <= io_cpu_req_bits_no_xcpt;
|
|
s1_tlb_req_vaddr <= s0_req_addr;
|
|
s1_tlb_req_size <= io_cpu_req_bits_size;
|
|
s1_tlb_req_cmd <= io_cpu_req_bits_cmd;
|
|
s1_tlb_req_prv <= io_cpu_req_bits_dprv;
|
|
s1_did_read <=
|
|
_dataArb_io_in_3_ready & io_cpu_req_valid
|
|
& (_pstore_drain_opportunistic_T | _pstore_drain_opportunistic_T_1
|
|
| _pstore_drain_opportunistic_T_2 | _pstore_drain_opportunistic_T_28
|
|
| _pstore_drain_opportunistic_T_30 | _pstore_drain_opportunistic_T_31
|
|
| _pstore_drain_opportunistic_T_32 | _pstore_drain_opportunistic_T_33
|
|
| _pstore_drain_opportunistic_T_37 | _pstore_drain_opportunistic_T_38
|
|
| _pstore_drain_opportunistic_T_39 | _pstore_drain_opportunistic_T_40
|
|
| _pstore_drain_opportunistic_T_41
|
|
| (_pstore_drain_opportunistic_T_25 | _pstore_drain_opportunistic_T_50
|
|
| _pstore_drain_opportunistic_T_28 | _pstore_drain_opportunistic_T_30
|
|
| _pstore_drain_opportunistic_T_31 | _pstore_drain_opportunistic_T_32
|
|
| _pstore_drain_opportunistic_T_33 | _pstore_drain_opportunistic_T_37
|
|
| _pstore_drain_opportunistic_T_38 | _pstore_drain_opportunistic_T_39
|
|
| _pstore_drain_opportunistic_T_40 | _pstore_drain_opportunistic_T_41)
|
|
& _pstore_drain_opportunistic_T_50);
|
|
end
|
|
if (_GEN_14) begin
|
|
uncachedReqs_0_addr <= s2_req_addr;
|
|
uncachedReqs_0_tag <= s2_req_tag;
|
|
uncachedReqs_0_size <= s2_req_size;
|
|
uncachedReqs_0_signed <= s2_req_signed;
|
|
end
|
|
s2_not_nacked_in_s1 <= ~s1_nack;
|
|
if (_GEN_10) begin
|
|
s2_req_addr <=
|
|
{2'h0, _tlb_io_resp_paddr[31:12], s1_req_addr[11:3], uncachedReqs_0_addr[2:0]};
|
|
s2_req_tag <= uncachedReqs_0_tag;
|
|
s2_req_cmd <= 5'h0;
|
|
s2_req_size <= uncachedReqs_0_size;
|
|
s2_req_signed <= uncachedReqs_0_signed;
|
|
end
|
|
else if (s1_valid_not_nacked) begin
|
|
s2_req_addr <= {2'h0, _tlb_io_resp_paddr[31:12], s1_req_addr[11:0]};
|
|
s2_req_tag <= s1_req_tag;
|
|
s2_req_cmd <= s1_req_cmd;
|
|
s2_req_size <= s1_req_size;
|
|
s2_req_signed <= s1_req_signed;
|
|
end
|
|
if (s1_valid_not_nacked) begin
|
|
s2_req_dprv <= s1_req_dprv;
|
|
s2_req_no_xcpt <= s1_req_no_xcpt;
|
|
s2_tlb_xcpt_pf_ld <= _tlb_io_resp_pf_ld;
|
|
s2_tlb_xcpt_pf_st <= _tlb_io_resp_pf_st;
|
|
s2_tlb_xcpt_ae_ld <= _tlb_io_resp_ae_ld;
|
|
s2_tlb_xcpt_ae_st <= _tlb_io_resp_ae_st;
|
|
s2_tlb_xcpt_ma_ld <= _tlb_io_resp_ma_ld;
|
|
s2_tlb_xcpt_ma_st <= _tlb_io_resp_ma_st;
|
|
s2_pma_cacheable <= _tlb_io_resp_cacheable;
|
|
s2_hit_state_state <=
|
|
{2{_tlb_io_resp_paddr[31]
|
|
& {_tlb_io_resp_paddr[31:12], s1_req_addr[11:0]} < 32'h80100000}};
|
|
end
|
|
if (s1_valid | io_cpu_replay_next_0) begin
|
|
automatic logic [1:0] _s2_data_T_1 =
|
|
io_cpu_replay_next_0 | s1_did_read ? (_GEN_10 ? 2'h2 : 2'h1) : 2'h0;
|
|
s2_data <=
|
|
(_s2_data_T_1[0] ? _data_io_resp_0 : 64'h0)
|
|
| (_s2_data_T_1[1] ? auto_out_d_bits_data : 64'h0);
|
|
end
|
|
if (s1_valid_not_nacked & s1_write) begin
|
|
pstore1_cmd <= s1_req_cmd;
|
|
pstore1_addr <= s1_req_addr;
|
|
pstore1_data <= io_cpu_s1_data_data;
|
|
pstore1_mask <=
|
|
_io_cpu_perf_canAcceptLoadThenLoad_T_51 ? io_cpu_s1_data_mask : s1_mask_xwr;
|
|
pstore1_rmw_r <=
|
|
_io_cpu_perf_canAcceptLoadThenLoad_T_1 | _io_cpu_perf_canAcceptLoadThenLoad_T_2
|
|
| _io_cpu_perf_canAcceptLoadThenLoad_T_3 | _io_cpu_perf_canAcceptLoadThenLoad_T_29
|
|
| _io_cpu_perf_canAcceptLoadThenLoad_T_31
|
|
| _io_cpu_perf_canAcceptLoadThenLoad_T_32
|
|
| _io_cpu_perf_canAcceptLoadThenLoad_T_33
|
|
| _io_cpu_perf_canAcceptLoadThenLoad_T_34
|
|
| _io_cpu_perf_canAcceptLoadThenLoad_T_38
|
|
| _io_cpu_perf_canAcceptLoadThenLoad_T_39
|
|
| _io_cpu_perf_canAcceptLoadThenLoad_T_40
|
|
| _io_cpu_perf_canAcceptLoadThenLoad_T_41
|
|
| _io_cpu_perf_canAcceptLoadThenLoad_T_42
|
|
| (_io_cpu_perf_canAcceptLoadThenLoad_T_26
|
|
| _io_cpu_perf_canAcceptLoadThenLoad_T_51
|
|
| _io_cpu_perf_canAcceptLoadThenLoad_T_29
|
|
| _io_cpu_perf_canAcceptLoadThenLoad_T_31
|
|
| _io_cpu_perf_canAcceptLoadThenLoad_T_32
|
|
| _io_cpu_perf_canAcceptLoadThenLoad_T_33
|
|
| _io_cpu_perf_canAcceptLoadThenLoad_T_34
|
|
| _io_cpu_perf_canAcceptLoadThenLoad_T_38
|
|
| _io_cpu_perf_canAcceptLoadThenLoad_T_39
|
|
| _io_cpu_perf_canAcceptLoadThenLoad_T_40
|
|
| _io_cpu_perf_canAcceptLoadThenLoad_T_41
|
|
| _io_cpu_perf_canAcceptLoadThenLoad_T_42)
|
|
& _io_cpu_perf_canAcceptLoadThenLoad_T_51;
|
|
end
|
|
pstore_drain_on_miss_REG <= io_cpu_s2_nack_0;
|
|
if (advance_pstore1) begin
|
|
pstore2_addr <= pstore1_addr;
|
|
pstore2_storegen_data_r <= pstore1_storegen_data[7:0];
|
|
pstore2_storegen_data_r_1 <= pstore1_storegen_data[15:8];
|
|
pstore2_storegen_data_r_2 <= pstore1_storegen_data[23:16];
|
|
pstore2_storegen_data_r_3 <= pstore1_storegen_data[31:24];
|
|
pstore2_storegen_data_r_4 <= pstore1_storegen_data[39:32];
|
|
pstore2_storegen_data_r_5 <= pstore1_storegen_data[47:40];
|
|
pstore2_storegen_data_r_6 <= pstore1_storegen_data[55:48];
|
|
pstore2_storegen_data_r_7 <= pstore1_storegen_data[63:56];
|
|
pstore2_storegen_mask <= pstore1_mask;
|
|
end
|
|
blockUncachedGrant <= _GEN_11 ? ~_dataArb_io_in_1_ready : _dataArb_io_out_valid;
|
|
io_cpu_s2_xcpt_REG <=
|
|
s1_valid & ~io_cpu_s1_kill
|
|
& (s1_read | s1_write | s1_req_cmd == 5'h5 & s1_req_size[0] | s1_req_cmd == 5'h17)
|
|
& ~s1_req_no_xcpt & ~s1_nack;
|
|
doUncachedResp <= io_cpu_replay_next_0;
|
|
end // always @(posedge)
|
|
DTLB tlb (
|
|
.io_req_bits_vaddr (s1_tlb_req_vaddr),
|
|
.io_req_bits_size (s1_tlb_req_size),
|
|
.io_req_bits_cmd (s1_tlb_req_cmd),
|
|
.io_req_bits_prv (s1_tlb_req_prv),
|
|
.io_resp_paddr (_tlb_io_resp_paddr),
|
|
.io_resp_pf_ld (_tlb_io_resp_pf_ld),
|
|
.io_resp_pf_st (_tlb_io_resp_pf_st),
|
|
.io_resp_ae_ld (_tlb_io_resp_ae_ld),
|
|
.io_resp_ae_st (_tlb_io_resp_ae_st),
|
|
.io_resp_ma_ld (_tlb_io_resp_ma_ld),
|
|
.io_resp_ma_st (_tlb_io_resp_ma_st),
|
|
.io_resp_cacheable (_tlb_io_resp_cacheable),
|
|
.io_ptw_status_debug (io_ptw_status_debug),
|
|
.io_ptw_pmp_0_cfg_l (io_ptw_pmp_0_cfg_l),
|
|
.io_ptw_pmp_0_cfg_a (io_ptw_pmp_0_cfg_a),
|
|
.io_ptw_pmp_0_cfg_w (io_ptw_pmp_0_cfg_w),
|
|
.io_ptw_pmp_0_cfg_r (io_ptw_pmp_0_cfg_r),
|
|
.io_ptw_pmp_0_addr (io_ptw_pmp_0_addr),
|
|
.io_ptw_pmp_0_mask (io_ptw_pmp_0_mask),
|
|
.io_ptw_pmp_1_cfg_l (io_ptw_pmp_1_cfg_l),
|
|
.io_ptw_pmp_1_cfg_a (io_ptw_pmp_1_cfg_a),
|
|
.io_ptw_pmp_1_cfg_w (io_ptw_pmp_1_cfg_w),
|
|
.io_ptw_pmp_1_cfg_r (io_ptw_pmp_1_cfg_r),
|
|
.io_ptw_pmp_1_addr (io_ptw_pmp_1_addr),
|
|
.io_ptw_pmp_1_mask (io_ptw_pmp_1_mask),
|
|
.io_ptw_pmp_2_cfg_l (io_ptw_pmp_2_cfg_l),
|
|
.io_ptw_pmp_2_cfg_a (io_ptw_pmp_2_cfg_a),
|
|
.io_ptw_pmp_2_cfg_w (io_ptw_pmp_2_cfg_w),
|
|
.io_ptw_pmp_2_cfg_r (io_ptw_pmp_2_cfg_r),
|
|
.io_ptw_pmp_2_addr (io_ptw_pmp_2_addr),
|
|
.io_ptw_pmp_2_mask (io_ptw_pmp_2_mask),
|
|
.io_ptw_pmp_3_cfg_l (io_ptw_pmp_3_cfg_l),
|
|
.io_ptw_pmp_3_cfg_a (io_ptw_pmp_3_cfg_a),
|
|
.io_ptw_pmp_3_cfg_w (io_ptw_pmp_3_cfg_w),
|
|
.io_ptw_pmp_3_cfg_r (io_ptw_pmp_3_cfg_r),
|
|
.io_ptw_pmp_3_addr (io_ptw_pmp_3_addr),
|
|
.io_ptw_pmp_3_mask (io_ptw_pmp_3_mask),
|
|
.io_ptw_pmp_4_cfg_l (io_ptw_pmp_4_cfg_l),
|
|
.io_ptw_pmp_4_cfg_a (io_ptw_pmp_4_cfg_a),
|
|
.io_ptw_pmp_4_cfg_w (io_ptw_pmp_4_cfg_w),
|
|
.io_ptw_pmp_4_cfg_r (io_ptw_pmp_4_cfg_r),
|
|
.io_ptw_pmp_4_addr (io_ptw_pmp_4_addr),
|
|
.io_ptw_pmp_4_mask (io_ptw_pmp_4_mask),
|
|
.io_ptw_pmp_5_cfg_l (io_ptw_pmp_5_cfg_l),
|
|
.io_ptw_pmp_5_cfg_a (io_ptw_pmp_5_cfg_a),
|
|
.io_ptw_pmp_5_cfg_w (io_ptw_pmp_5_cfg_w),
|
|
.io_ptw_pmp_5_cfg_r (io_ptw_pmp_5_cfg_r),
|
|
.io_ptw_pmp_5_addr (io_ptw_pmp_5_addr),
|
|
.io_ptw_pmp_5_mask (io_ptw_pmp_5_mask),
|
|
.io_ptw_pmp_6_cfg_l (io_ptw_pmp_6_cfg_l),
|
|
.io_ptw_pmp_6_cfg_a (io_ptw_pmp_6_cfg_a),
|
|
.io_ptw_pmp_6_cfg_w (io_ptw_pmp_6_cfg_w),
|
|
.io_ptw_pmp_6_cfg_r (io_ptw_pmp_6_cfg_r),
|
|
.io_ptw_pmp_6_addr (io_ptw_pmp_6_addr),
|
|
.io_ptw_pmp_6_mask (io_ptw_pmp_6_mask),
|
|
.io_ptw_pmp_7_cfg_l (io_ptw_pmp_7_cfg_l),
|
|
.io_ptw_pmp_7_cfg_a (io_ptw_pmp_7_cfg_a),
|
|
.io_ptw_pmp_7_cfg_w (io_ptw_pmp_7_cfg_w),
|
|
.io_ptw_pmp_7_cfg_r (io_ptw_pmp_7_cfg_r),
|
|
.io_ptw_pmp_7_addr (io_ptw_pmp_7_addr),
|
|
.io_ptw_pmp_7_mask (io_ptw_pmp_7_mask)
|
|
);
|
|
Arbiter8_DCacheMetadataReq metaArb (
|
|
.io_in_2_valid (metaArb_io_in_2_valid),
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.io_in_2_bits_addr ({io_cpu_req_bits_addr[33:20], s2_req_addr[19:0]}),
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.io_in_3_valid (1'h0),
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.io_in_3_bits_addr ({io_cpu_req_bits_addr[33:20], s2_req_addr[19:0]}),
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.io_in_7_ready (_metaArb_io_in_7_ready),
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.io_in_7_valid (io_cpu_req_valid),
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.io_in_7_bits_addr (io_cpu_req_bits_addr),
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.io_out_valid (_metaArb_io_out_valid),
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.io_out_bits_write (_metaArb_io_out_bits_write),
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.io_out_bits_addr (_metaArb_io_out_bits_addr)
|
|
);
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DCacheDataArray data (
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.clock (clock),
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.io_req_valid (_dataArb_io_out_valid),
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.io_req_bits_addr (_dataArb_io_out_bits_addr),
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|
.io_req_bits_write (_dataArb_io_out_bits_write),
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|
.io_req_bits_wdata (_dataArb_io_out_bits_wdata),
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.io_req_bits_eccMask (_dataArb_io_out_bits_eccMask),
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|
.io_resp_0 (_data_io_resp_0)
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|
);
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|
Arbiter4_DCacheDataReq dataArb (
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|
.io_in_0_valid
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|
(pstore_drain_structural
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| ((_dataArb_io_in_0_valid_T_4 | pstore1_held) & ~pstore1_rmw_r | pstore2_valid)
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|
& _dataArb_io_in_0_valid_T_9),
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|
.io_in_0_bits_addr (_dataArb_io_in_0_bits_wordMask_wordMask_T),
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|
.io_in_0_bits_write (dataArb_io_in_0_bits_write),
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|
.io_in_0_bits_wdata (dataArb_io_in_3_bits_wdata),
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|
.io_in_0_bits_eccMask (dataArb_io_in_1_bits_eccMask),
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|
.io_in_1_ready (_dataArb_io_in_1_ready),
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|
.io_in_1_valid (_GEN_11),
|
|
.io_in_1_bits_addr (_dataArb_io_in_0_bits_wordMask_wordMask_T),
|
|
.io_in_1_bits_write (~_GEN_11 & dataArb_io_in_0_bits_write),
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|
.io_in_1_bits_wdata (dataArb_io_in_3_bits_wdata),
|
|
.io_in_1_bits_eccMask (dataArb_io_in_1_bits_eccMask),
|
|
.io_in_3_ready (_dataArb_io_in_3_ready),
|
|
.io_in_3_valid (io_cpu_req_valid & ~_dataArb_io_in_3_valid_res_T_2),
|
|
.io_in_3_bits_addr (io_cpu_req_bits_addr[19:0]),
|
|
.io_in_3_bits_wdata (dataArb_io_in_3_bits_wdata),
|
|
.io_out_valid (_dataArb_io_out_valid),
|
|
.io_out_bits_addr (_dataArb_io_out_bits_addr),
|
|
.io_out_bits_write (_dataArb_io_out_bits_write),
|
|
.io_out_bits_wdata (_dataArb_io_out_bits_wdata),
|
|
.io_out_bits_eccMask (_dataArb_io_out_bits_eccMask)
|
|
);
|
|
AMOALU amoalus_0 (
|
|
.io_mask (pstore1_mask),
|
|
.io_cmd (pstore1_cmd),
|
|
.io_lhs (s2_data),
|
|
.io_rhs (pstore1_data),
|
|
.io_out_unmasked (_amoalus_0_io_out_unmasked)
|
|
);
|
|
assign auto_out_a_valid = tl_out_a_valid;
|
|
assign auto_out_a_bits_opcode =
|
|
s2_pma_cacheable
|
|
? 3'h0
|
|
: s2_write
|
|
? (_io_cpu_store_pending_T_1
|
|
? 3'h1
|
|
: s2_read
|
|
? (_io_cpu_store_pending_T_16 | _io_cpu_store_pending_T_15
|
|
| _io_cpu_store_pending_T_14 | _io_cpu_store_pending_T_13
|
|
| _io_cpu_store_pending_T_12
|
|
? 3'h2
|
|
: _GEN_5 ? 3'h3 : 3'h0)
|
|
: 3'h0)
|
|
: 3'h4;
|
|
assign auto_out_a_bits_param =
|
|
s2_pma_cacheable | ~s2_write | _io_cpu_store_pending_T_1 | ~s2_read
|
|
? 3'h0
|
|
: _io_cpu_store_pending_T_16
|
|
? 3'h3
|
|
: _io_cpu_store_pending_T_15
|
|
? 3'h2
|
|
: _io_cpu_store_pending_T_14
|
|
? 3'h1
|
|
: _io_cpu_store_pending_T_13
|
|
? 3'h0
|
|
: _io_cpu_store_pending_T_12
|
|
? 3'h4
|
|
: _io_cpu_store_pending_T_8
|
|
? 3'h2
|
|
: _io_cpu_store_pending_T_7
|
|
? 3'h1
|
|
: _io_cpu_store_pending_T_6 | ~_io_cpu_store_pending_T_5
|
|
? 3'h0
|
|
: 3'h3;
|
|
assign auto_out_a_bits_size = _GEN_7 ? 4'h0 : _GEN_4;
|
|
assign auto_out_a_bits_address = _GEN_7 ? 32'h0 : s2_req_addr[31:0];
|
|
assign auto_out_a_bits_user_amba_prot_bufferable = s2_pma_cacheable;
|
|
assign auto_out_a_bits_user_amba_prot_modifiable = s2_pma_cacheable;
|
|
assign auto_out_a_bits_user_amba_prot_readalloc = s2_pma_cacheable;
|
|
assign auto_out_a_bits_user_amba_prot_writealloc = s2_pma_cacheable;
|
|
assign auto_out_a_bits_user_amba_prot_privileged = (&s2_req_dprv) | s2_pma_cacheable;
|
|
assign auto_out_a_bits_mask =
|
|
s2_pma_cacheable
|
|
? 8'h0
|
|
: s2_write
|
|
? (_io_cpu_store_pending_T_1
|
|
? pstore1_mask
|
|
: s2_read
|
|
? atomics_mask
|
|
: {put_a_mask_sub_3_1 | put_a_mask_sub_3_2 & s2_req_addr[0],
|
|
put_a_mask_sub_3_1 | put_a_mask_sub_3_2 & ~(s2_req_addr[0]),
|
|
put_a_mask_sub_2_1 | put_a_mask_sub_2_2 & s2_req_addr[0],
|
|
put_a_mask_sub_2_1 | put_a_mask_sub_2_2 & ~(s2_req_addr[0]),
|
|
put_a_mask_sub_1_1 | put_a_mask_sub_1_2 & s2_req_addr[0],
|
|
put_a_mask_sub_1_1 | put_a_mask_sub_1_2 & ~(s2_req_addr[0]),
|
|
put_a_mask_sub_0_1 | put_a_mask_sub_0_2 & s2_req_addr[0],
|
|
put_a_mask_sub_0_1 | put_a_mask_sub_0_2 & ~(s2_req_addr[0])})
|
|
: {get_a_mask_sub_3_1 | get_a_mask_sub_3_2 & s2_req_addr[0],
|
|
get_a_mask_sub_3_1 | get_a_mask_sub_3_2 & ~(s2_req_addr[0]),
|
|
get_a_mask_sub_2_1 | get_a_mask_sub_2_2 & s2_req_addr[0],
|
|
get_a_mask_sub_2_1 | get_a_mask_sub_2_2 & ~(s2_req_addr[0]),
|
|
get_a_mask_sub_1_1 | get_a_mask_sub_1_2 & s2_req_addr[0],
|
|
get_a_mask_sub_1_1 | get_a_mask_sub_1_2 & ~(s2_req_addr[0]),
|
|
get_a_mask_sub_0_1 | get_a_mask_sub_0_2 & s2_req_addr[0],
|
|
get_a_mask_sub_0_1 | get_a_mask_sub_0_2 & ~(s2_req_addr[0])};
|
|
assign auto_out_a_bits_data =
|
|
s2_pma_cacheable | ~s2_write | ~_GEN_6 ? 64'h0 : pstore1_data;
|
|
assign auto_out_d_ready = ~_GEN;
|
|
assign io_cpu_req_ready = io_cpu_req_ready_0;
|
|
assign io_cpu_s2_nack = io_cpu_s2_nack_0;
|
|
assign io_cpu_resp_valid = s2_valid_hit_pre_data_ecc_and_waw | doUncachedResp;
|
|
assign io_cpu_resp_bits_tag = s2_req_tag;
|
|
assign io_cpu_resp_bits_size = s2_req_size;
|
|
assign io_cpu_resp_bits_data =
|
|
{s2_req_size == 2'h0
|
|
? {56{s2_req_signed & io_cpu_resp_bits_data_zeroed_2[7]}}
|
|
: {s2_req_size == 2'h1
|
|
? {48{s2_req_signed & io_cpu_resp_bits_data_zeroed_1[15]}}
|
|
: {_io_cpu_resp_bits_data_word_bypass_T_1
|
|
? {32{s2_req_signed & io_cpu_resp_bits_data_zeroed[31]}}
|
|
: s2_data[63:32],
|
|
io_cpu_resp_bits_data_zeroed[31:16]},
|
|
io_cpu_resp_bits_data_zeroed_1[15:8]},
|
|
io_cpu_resp_bits_data_zeroed_2};
|
|
assign io_cpu_resp_bits_replay = doUncachedResp;
|
|
assign io_cpu_resp_bits_has_data = s2_read;
|
|
assign io_cpu_resp_bits_data_word_bypass =
|
|
{_io_cpu_resp_bits_data_word_bypass_T_1
|
|
? {32{s2_req_signed & io_cpu_resp_bits_data_word_bypass_zeroed[31]}}
|
|
: s2_data[63:32],
|
|
io_cpu_resp_bits_data_word_bypass_zeroed};
|
|
assign io_cpu_resp_bits_data_raw = s2_data;
|
|
assign io_cpu_replay_next = io_cpu_replay_next_0;
|
|
assign io_cpu_s2_xcpt_ma_ld = io_cpu_s2_xcpt_ma_ld_0;
|
|
assign io_cpu_s2_xcpt_ma_st = io_cpu_s2_xcpt_ma_st_0;
|
|
assign io_cpu_s2_xcpt_pf_ld = io_cpu_s2_xcpt_pf_ld_0;
|
|
assign io_cpu_s2_xcpt_pf_st = io_cpu_s2_xcpt_pf_st_0;
|
|
assign io_cpu_s2_xcpt_ae_ld = io_cpu_s2_xcpt_ae_ld_0;
|
|
assign io_cpu_s2_xcpt_ae_st = io_cpu_s2_xcpt_ae_st_0;
|
|
assign io_cpu_ordered =
|
|
~(s1_valid & ~s1_req_no_xcpt | s2_valid & ~s2_req_no_xcpt | cached_grant_wait
|
|
| uncachedInFlight_0);
|
|
assign io_cpu_perf_grant = auto_out_d_valid & d_last;
|
|
endmodule
|
|
|