onur
13 lines
257 B
Systemverilog
13 lines
257 B
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module IntSyncSyncCrossingSink_n1x2(
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input auto_in_sync_0,
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auto_in_sync_1,
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output auto_out_0,
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auto_out_1
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);
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assign auto_out_0 = auto_in_sync_0;
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assign auto_out_1 = auto_in_sync_1;
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endmodule
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