onur
21 lines
458 B
Systemverilog
21 lines
458 B
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module LevelGateway(
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input clock,
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reset,
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io_interrupt,
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output io_plic_valid,
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input io_plic_ready,
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io_plic_complete
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);
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reg inFlight;
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always @(posedge clock) begin
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if (reset)
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inFlight <= 1'h0;
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else
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inFlight <= ~io_plic_complete & (io_interrupt & io_plic_ready | inFlight);
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end // always @(posedge)
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assign io_plic_valid = io_interrupt & ~inFlight;
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endmodule
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