onur
205 lines
11 KiB
Systemverilog
205 lines
11 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module MulAddRecFNPipe_l2_e8_s24(
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input clock,
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reset,
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io_validin,
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input [1:0] io_op,
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input [32:0] io_a,
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io_b,
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io_c,
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input [2:0] io_roundingMode,
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output [32:0] io_out,
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output [4:0] io_exceptionFlags
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);
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wire _mulAddRecFNToRaw_postMul_io_invalidExc;
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wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN;
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wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf;
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wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero;
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wire _mulAddRecFNToRaw_postMul_io_rawOut_sign;
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wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp;
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wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig;
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wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA;
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wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddB;
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wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC;
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wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny;
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wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB;
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wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA;
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wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA;
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wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB;
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wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB;
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wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd;
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wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC;
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wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC;
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wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC;
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wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum;
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wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags;
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wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant;
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wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist;
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wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC;
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wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC;
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reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny;
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reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB;
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reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA;
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reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA;
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reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB;
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reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB;
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reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd;
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reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC;
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reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC;
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reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC;
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reg [9:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum;
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reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags;
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reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant;
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reg [4:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist;
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reg [25:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC;
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reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC;
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reg [48:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b;
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reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b;
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reg [2:0] roundingMode_stage0_pipe_b;
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reg valid_stage0_pipe_v;
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reg roundRawFNToRecFN_io_invalidExc_pipe_b;
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reg roundRawFNToRecFN_io_in_pipe_b_isNaN;
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reg roundRawFNToRecFN_io_in_pipe_b_isInf;
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reg roundRawFNToRecFN_io_in_pipe_b_isZero;
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reg roundRawFNToRecFN_io_in_pipe_b_sign;
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reg [9:0] roundRawFNToRecFN_io_in_pipe_b_sExp;
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reg [26:0] roundRawFNToRecFN_io_in_pipe_b_sig;
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reg [2:0] roundRawFNToRecFN_io_roundingMode_pipe_b;
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always @(posedge clock) begin
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if (io_validin) begin
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mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny <=
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_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny;
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mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB <=
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_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB;
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mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA <=
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_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA;
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mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA <=
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_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA;
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mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB <=
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_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB;
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mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB <=
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_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB;
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mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd <=
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_mulAddRecFNToRaw_preMul_io_toPostMul_signProd;
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mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC <=
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_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC;
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mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC <=
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_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC;
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mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC <=
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_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC;
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mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum <=
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_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum;
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mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags <=
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_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags;
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mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant <=
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_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant;
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mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist <=
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_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist;
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mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC <=
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_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC;
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mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC <=
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_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC;
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mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b <=
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{1'h0,
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{24'h0, _mulAddRecFNToRaw_preMul_io_mulAddA}
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* {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}}
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+ {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC};
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mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b <= io_roundingMode;
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roundingMode_stage0_pipe_b <= io_roundingMode;
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end
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if (valid_stage0_pipe_v) begin
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roundRawFNToRecFN_io_invalidExc_pipe_b <= _mulAddRecFNToRaw_postMul_io_invalidExc;
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roundRawFNToRecFN_io_in_pipe_b_isNaN <= _mulAddRecFNToRaw_postMul_io_rawOut_isNaN;
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roundRawFNToRecFN_io_in_pipe_b_isInf <= _mulAddRecFNToRaw_postMul_io_rawOut_isInf;
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roundRawFNToRecFN_io_in_pipe_b_isZero <= _mulAddRecFNToRaw_postMul_io_rawOut_isZero;
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roundRawFNToRecFN_io_in_pipe_b_sign <= _mulAddRecFNToRaw_postMul_io_rawOut_sign;
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roundRawFNToRecFN_io_in_pipe_b_sExp <= _mulAddRecFNToRaw_postMul_io_rawOut_sExp;
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roundRawFNToRecFN_io_in_pipe_b_sig <= _mulAddRecFNToRaw_postMul_io_rawOut_sig;
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roundRawFNToRecFN_io_roundingMode_pipe_b <= roundingMode_stage0_pipe_b;
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end
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if (reset)
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valid_stage0_pipe_v <= 1'h0;
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else
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valid_stage0_pipe_v <= io_validin;
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end // always @(posedge)
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MulAddRecFNToRaw_preMul mulAddRecFNToRaw_preMul (
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.io_op (io_op),
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.io_a (io_a),
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.io_b (io_b),
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.io_c (io_c),
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.io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),
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.io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB),
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.io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),
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.io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),
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.io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),
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.io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),
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.io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),
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.io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB),
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.io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB),
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.io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),
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.io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC),
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.io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC),
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.io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC),
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.io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),
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.io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),
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.io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant),
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.io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),
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.io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),
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.io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)
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);
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MulAddRecFNToRaw_postMul mulAddRecFNToRaw_postMul (
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.io_fromPreMul_isSigNaNAny
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(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny),
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.io_fromPreMul_isNaNAOrB
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(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB),
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.io_fromPreMul_isInfA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA),
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.io_fromPreMul_isZeroA
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(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA),
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.io_fromPreMul_isInfB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB),
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.io_fromPreMul_isZeroB
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(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB),
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.io_fromPreMul_signProd
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(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd),
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.io_fromPreMul_isNaNC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC),
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.io_fromPreMul_isInfC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC),
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.io_fromPreMul_isZeroC
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(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC),
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.io_fromPreMul_sExpSum
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(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum),
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.io_fromPreMul_doSubMags
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(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags),
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.io_fromPreMul_CIsDominant
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(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant),
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.io_fromPreMul_CDom_CAlignDist
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(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist),
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.io_fromPreMul_highAlignedSigC
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(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC),
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.io_fromPreMul_bit0AlignedSigC
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(mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC),
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.io_mulAddResult (mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b),
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.io_roundingMode (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b),
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.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),
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.io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),
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.io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),
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.io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),
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.io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),
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.io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),
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.io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)
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);
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RoundRawFNToRecFN roundRawFNToRecFN (
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.io_invalidExc (roundRawFNToRecFN_io_invalidExc_pipe_b),
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.io_infiniteExc (1'h0),
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.io_in_isNaN (roundRawFNToRecFN_io_in_pipe_b_isNaN),
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.io_in_isInf (roundRawFNToRecFN_io_in_pipe_b_isInf),
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.io_in_isZero (roundRawFNToRecFN_io_in_pipe_b_isZero),
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.io_in_sign (roundRawFNToRecFN_io_in_pipe_b_sign),
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.io_in_sExp (roundRawFNToRecFN_io_in_pipe_b_sExp),
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.io_in_sig (roundRawFNToRecFN_io_in_pipe_b_sig),
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.io_roundingMode (roundRawFNToRecFN_io_roundingMode_pipe_b),
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.io_out (io_out),
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.io_exceptionFlags (io_exceptionFlags)
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);
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endmodule
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