onur
93 lines
3.8 KiB
Systemverilog
93 lines
3.8 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module MulAddRecFNToRaw_preMul(
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input [1:0] io_op,
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input [32:0] io_a,
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io_b,
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io_c,
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output [23:0] io_mulAddA,
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io_mulAddB,
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output [47:0] io_mulAddC,
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output io_toPostMul_isSigNaNAny,
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io_toPostMul_isNaNAOrB,
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io_toPostMul_isInfA,
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io_toPostMul_isZeroA,
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io_toPostMul_isInfB,
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io_toPostMul_isZeroB,
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io_toPostMul_signProd,
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io_toPostMul_isNaNC,
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io_toPostMul_isInfC,
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io_toPostMul_isZeroC,
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output [9:0] io_toPostMul_sExpSum,
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output io_toPostMul_doSubMags,
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io_toPostMul_CIsDominant,
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output [4:0] io_toPostMul_CDom_CAlignDist,
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output [25:0] io_toPostMul_highAlignedSigC,
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output io_toPostMul_bit0AlignedSigC
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);
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wire _rawA_out_sig_T = |(io_a[31:29]);
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wire rawA_isSpecial = &(io_a[31:30]);
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wire rawA_isNaN = rawA_isSpecial & io_a[29];
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wire _rawB_out_sig_T = |(io_b[31:29]);
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wire rawB_isSpecial = &(io_b[31:30]);
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wire rawB_isNaN = rawB_isSpecial & io_b[29];
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wire _rawC_out_sig_T = |(io_c[31:29]);
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wire rawC_isSpecial = &(io_c[31:30]);
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wire rawC_isNaN = rawC_isSpecial & io_c[29];
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wire signProd = io_a[32] ^ io_b[32] ^ io_op[1];
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wire [10:0] _sExpAlignedProd_T_1 = {2'h0, io_a[31:23]} + {2'h0, io_b[31:23]} - 11'hE5;
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wire doSubMags = signProd ^ io_c[32] ^ io_op[0];
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wire [10:0] _sNatCAlignDist_T = _sExpAlignedProd_T_1 - {2'h0, io_c[31:23]};
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wire isMinCAlign =
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~_rawA_out_sig_T | ~_rawB_out_sig_T | $signed(_sNatCAlignDist_T) < 11'sh0;
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wire CIsDominant =
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_rawC_out_sig_T & (isMinCAlign | _sNatCAlignDist_T[9:0] < 10'h19);
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wire [6:0] CAlignDist =
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isMinCAlign ? 7'h0 : _sNatCAlignDist_T[9:0] < 10'h4A ? _sNatCAlignDist_T[6:0] : 7'h4A;
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wire [77:0] mainAlignedSigC =
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$unsigned($signed($signed({doSubMags
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? {1'h1, ~_rawC_out_sig_T, ~(io_c[22:0])}
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: {1'h0, _rawC_out_sig_T, io_c[22:0]},
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{53{doSubMags}}}) >>> CAlignDist));
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wire [32:0] reduced4CExtra_shift =
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$unsigned($signed(33'sh100000000 >>> CAlignDist[6:2]));
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wire [5:0] _GEN =
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{|(io_c[21:18]),
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|(io_c[17:14]),
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|(io_c[13:10]),
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|(io_c[9:6]),
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|(io_c[5:2]),
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|(io_c[1:0])}
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& {reduced4CExtra_shift[14],
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reduced4CExtra_shift[15],
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reduced4CExtra_shift[16],
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reduced4CExtra_shift[17],
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reduced4CExtra_shift[18],
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reduced4CExtra_shift[19]};
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assign io_mulAddA = {_rawA_out_sig_T, io_a[22:0]};
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assign io_mulAddB = {_rawB_out_sig_T, io_b[22:0]};
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assign io_mulAddC = mainAlignedSigC[50:3];
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assign io_toPostMul_isSigNaNAny =
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rawA_isNaN & ~(io_a[22]) | rawB_isNaN & ~(io_b[22]) | rawC_isNaN & ~(io_c[22]);
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assign io_toPostMul_isNaNAOrB = rawA_isNaN | rawB_isNaN;
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assign io_toPostMul_isInfA = rawA_isSpecial & ~(io_a[29]);
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assign io_toPostMul_isZeroA = ~_rawA_out_sig_T;
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assign io_toPostMul_isInfB = rawB_isSpecial & ~(io_b[29]);
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assign io_toPostMul_isZeroB = ~_rawB_out_sig_T;
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assign io_toPostMul_signProd = signProd;
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assign io_toPostMul_isNaNC = rawC_isNaN;
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assign io_toPostMul_isInfC = rawC_isSpecial & ~(io_c[29]);
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assign io_toPostMul_isZeroC = ~_rawC_out_sig_T;
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assign io_toPostMul_sExpSum =
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CIsDominant ? {1'h0, io_c[31:23]} : _sExpAlignedProd_T_1[9:0] - 10'h18;
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assign io_toPostMul_doSubMags = doSubMags;
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assign io_toPostMul_CIsDominant = CIsDominant;
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assign io_toPostMul_CDom_CAlignDist = CAlignDist[4:0];
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assign io_toPostMul_highAlignedSigC = mainAlignedSigC[76:51];
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assign io_toPostMul_bit0AlignedSigC =
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doSubMags
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? (&(mainAlignedSigC[2:0])) & _GEN == 6'h0
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: (|{mainAlignedSigC[2:0], _GEN});
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endmodule
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