onur
37 lines
1.1 KiB
Systemverilog
37 lines
1.1 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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// Users can define 'PRINTF_COND' to add an extra gate to prints.
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`ifndef PRINTF_COND_
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`ifdef PRINTF_COND
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`define PRINTF_COND_ (`PRINTF_COND)
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`else // PRINTF_COND
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`define PRINTF_COND_ 1
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`endif // PRINTF_COND
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`endif // not def PRINTF_COND_
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module PlusArgTimeout(
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input clock,
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reset,
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input [31:0] io_count
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);
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wire [31:0] _plusarg_reader_out;
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wire _GEN = (|_plusarg_reader_out) & ~reset;
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`ifndef SYNTHESIS
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always @(posedge clock) begin
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if ((`PRINTF_COND_) & _GEN & io_count >= _plusarg_reader_out)
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$fwrite(32'h80000002,
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"Assertion failed: Timeout exceeded: Kill the emulation after INT rdtime cycles. Off if 0.\n at PlusArg.scala:64 assert (io.count < max, s\"Timeout exceeded: $docstring\")\n");
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end // always @(posedge)
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`endif // not def SYNTHESIS
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always @(posedge clock) begin
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end // always @(posedge)
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plusarg_reader #(
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.DEFAULT(0),
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.FORMAT("max_core_cycles=%d"),
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.WIDTH(32)
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) plusarg_reader (
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.out (_plusarg_reader_out)
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);
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endmodule
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