onur
51 lines
1.6 KiB
Systemverilog
51 lines
1.6 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module Queue1_RegMapperInput_i9_m8(
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input clock,
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reset,
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output io_enq_ready,
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input io_enq_valid,
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io_enq_bits_read,
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input [8:0] io_enq_bits_index,
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input [63:0] io_enq_bits_data,
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input [7:0] io_enq_bits_mask,
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input [5:0] io_enq_bits_extra_tlrr_extra_source,
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input [1:0] io_enq_bits_extra_tlrr_extra_size,
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input io_deq_ready,
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output io_deq_valid,
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io_deq_bits_read,
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output [8:0] io_deq_bits_index,
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output [63:0] io_deq_bits_data,
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output [7:0] io_deq_bits_mask,
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output [5:0] io_deq_bits_extra_tlrr_extra_source,
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output [1:0] io_deq_bits_extra_tlrr_extra_size
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);
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reg [89:0] ram;
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reg maybe_full;
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always @(posedge clock) begin
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automatic logic do_enq;
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do_enq = ~maybe_full & io_enq_valid;
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if (reset)
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maybe_full <= 1'h0;
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else if (do_enq != (io_deq_ready & maybe_full))
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maybe_full <= do_enq;
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if (do_enq)
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ram <=
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{io_enq_bits_read,
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io_enq_bits_index,
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io_enq_bits_data,
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io_enq_bits_mask,
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io_enq_bits_extra_tlrr_extra_source,
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io_enq_bits_extra_tlrr_extra_size};
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end // always @(posedge)
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assign io_enq_ready = ~maybe_full;
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assign io_deq_valid = maybe_full;
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assign io_deq_bits_read = ram[89];
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assign io_deq_bits_index = ram[88:80];
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assign io_deq_bits_data = ram[79:16];
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assign io_deq_bits_mask = ram[15:8];
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assign io_deq_bits_extra_tlrr_extra_source = ram[7:2];
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assign io_deq_bits_extra_tlrr_extra_size = ram[1:0];
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endmodule
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