onur
41 lines
1.7 KiB
Systemverilog
41 lines
1.7 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module RecFNToIN_1(
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input [64:0] io_in,
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input [2:0] io_roundingMode,
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input io_signedOut,
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output [2:0] io_intExceptionFlags
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);
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wire rawIn_isSpecial = &(io_in[63:62]);
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wire magJustBelowOne = ~(io_in[63]) & (&(io_in[62:52]));
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wire [83:0] shiftedSig =
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{31'h0, io_in[63], io_in[51:0]} << (io_in[63] ? io_in[56:52] : 5'h0);
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wire [1:0] _roundIncr_near_even_T_6 = {shiftedSig[51], |(shiftedSig[50:0])};
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wire common_inexact =
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io_in[63] ? (|_roundIncr_near_even_T_6) : (|(io_in[63:61]));
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wire roundIncr =
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io_roundingMode == 3'h0
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& (io_in[63] & ((&(shiftedSig[52:51])) | (&_roundIncr_near_even_T_6))
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| magJustBelowOne & (|_roundIncr_near_even_T_6)) | io_roundingMode == 3'h4
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& (io_in[63] & shiftedSig[51] | magJustBelowOne)
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| (io_roundingMode == 3'h2 | io_roundingMode == 3'h6) & io_in[64] & common_inexact
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| io_roundingMode == 3'h3 & ~(io_in[64]) & common_inexact;
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wire magGeOne_atOverflowEdge = io_in[62:52] == 11'h1F;
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wire roundCarryBut2 = (&(shiftedSig[81:52])) & roundIncr;
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wire common_overflow =
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io_in[63]
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? (|(io_in[62:57]))
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| (io_signedOut
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? (io_in[64]
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? magGeOne_atOverflowEdge & ((|(shiftedSig[82:52])) | roundIncr)
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: magGeOne_atOverflowEdge | io_in[62:52] == 11'h1E & roundCarryBut2)
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: io_in[64] | magGeOne_atOverflowEdge & shiftedSig[82] & roundCarryBut2)
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: ~io_signedOut & io_in[64] & roundIncr;
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wire invalidExc = rawIn_isSpecial & io_in[61] | rawIn_isSpecial & ~(io_in[61]);
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assign io_intExceptionFlags =
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{invalidExc,
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~invalidExc & common_overflow,
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~invalidExc & ~common_overflow & common_inexact};
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endmodule
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