onur
3191 lines
148 KiB
Systemverilog
3191 lines
148 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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// Users can define 'PRINTF_COND' to add an extra gate to prints.
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`ifndef PRINTF_COND_
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`ifdef PRINTF_COND
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`define PRINTF_COND_ (`PRINTF_COND)
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`else // PRINTF_COND
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`define PRINTF_COND_ 1
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`endif // PRINTF_COND
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`endif // not def PRINTF_COND_
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module Rocket(
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input clock,
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reset,
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io_interrupts_debug,
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io_interrupts_mtip,
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io_interrupts_msip,
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io_interrupts_meip,
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output io_imem_might_request,
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io_imem_req_valid,
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output [33:0] io_imem_req_bits_pc,
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output io_imem_req_bits_speculative,
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io_imem_resp_ready,
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input io_imem_resp_valid,
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input [33:0] io_imem_resp_bits_pc,
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input [31:0] io_imem_resp_bits_data,
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input io_imem_resp_bits_xcpt_pf_inst,
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io_imem_resp_bits_xcpt_gf_inst,
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io_imem_resp_bits_xcpt_ae_inst,
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io_imem_resp_bits_replay,
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output io_imem_btb_update_valid,
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io_imem_bht_update_valid,
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io_imem_flush_icache,
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input io_dmem_req_ready,
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output io_dmem_req_valid,
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output [33:0] io_dmem_req_bits_addr,
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output [6:0] io_dmem_req_bits_tag,
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output [4:0] io_dmem_req_bits_cmd,
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output [1:0] io_dmem_req_bits_size,
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output io_dmem_req_bits_signed,
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io_dmem_s1_kill,
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output [63:0] io_dmem_s1_data_data,
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input io_dmem_s2_nack,
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io_dmem_resp_valid,
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input [6:0] io_dmem_resp_bits_tag,
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input [1:0] io_dmem_resp_bits_size,
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input [63:0] io_dmem_resp_bits_data,
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input io_dmem_resp_bits_replay,
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io_dmem_resp_bits_has_data,
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input [63:0] io_dmem_resp_bits_data_word_bypass,
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input io_dmem_replay_next,
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io_dmem_s2_xcpt_ma_ld,
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io_dmem_s2_xcpt_ma_st,
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io_dmem_s2_xcpt_pf_ld,
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io_dmem_s2_xcpt_pf_st,
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io_dmem_s2_xcpt_ae_ld,
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io_dmem_s2_xcpt_ae_st,
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io_dmem_ordered,
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io_dmem_perf_grant,
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output io_ptw_status_debug,
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io_ptw_pmp_0_cfg_l,
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output [1:0] io_ptw_pmp_0_cfg_a,
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output io_ptw_pmp_0_cfg_x,
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io_ptw_pmp_0_cfg_w,
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io_ptw_pmp_0_cfg_r,
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output [29:0] io_ptw_pmp_0_addr,
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output [31:0] io_ptw_pmp_0_mask,
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output io_ptw_pmp_1_cfg_l,
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output [1:0] io_ptw_pmp_1_cfg_a,
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output io_ptw_pmp_1_cfg_x,
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io_ptw_pmp_1_cfg_w,
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io_ptw_pmp_1_cfg_r,
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output [29:0] io_ptw_pmp_1_addr,
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output [31:0] io_ptw_pmp_1_mask,
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output io_ptw_pmp_2_cfg_l,
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output [1:0] io_ptw_pmp_2_cfg_a,
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output io_ptw_pmp_2_cfg_x,
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io_ptw_pmp_2_cfg_w,
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io_ptw_pmp_2_cfg_r,
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output [29:0] io_ptw_pmp_2_addr,
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output [31:0] io_ptw_pmp_2_mask,
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output io_ptw_pmp_3_cfg_l,
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output [1:0] io_ptw_pmp_3_cfg_a,
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output io_ptw_pmp_3_cfg_x,
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io_ptw_pmp_3_cfg_w,
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io_ptw_pmp_3_cfg_r,
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output [29:0] io_ptw_pmp_3_addr,
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output [31:0] io_ptw_pmp_3_mask,
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output io_ptw_pmp_4_cfg_l,
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output [1:0] io_ptw_pmp_4_cfg_a,
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output io_ptw_pmp_4_cfg_x,
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io_ptw_pmp_4_cfg_w,
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io_ptw_pmp_4_cfg_r,
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output [29:0] io_ptw_pmp_4_addr,
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output [31:0] io_ptw_pmp_4_mask,
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output io_ptw_pmp_5_cfg_l,
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output [1:0] io_ptw_pmp_5_cfg_a,
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output io_ptw_pmp_5_cfg_x,
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io_ptw_pmp_5_cfg_w,
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io_ptw_pmp_5_cfg_r,
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output [29:0] io_ptw_pmp_5_addr,
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output [31:0] io_ptw_pmp_5_mask,
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output io_ptw_pmp_6_cfg_l,
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output [1:0] io_ptw_pmp_6_cfg_a,
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output io_ptw_pmp_6_cfg_x,
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io_ptw_pmp_6_cfg_w,
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io_ptw_pmp_6_cfg_r,
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output [29:0] io_ptw_pmp_6_addr,
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output [31:0] io_ptw_pmp_6_mask,
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output io_ptw_pmp_7_cfg_l,
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output [1:0] io_ptw_pmp_7_cfg_a,
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output io_ptw_pmp_7_cfg_x,
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io_ptw_pmp_7_cfg_w,
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io_ptw_pmp_7_cfg_r,
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output [29:0] io_ptw_pmp_7_addr,
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output [31:0] io_ptw_pmp_7_mask,
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output [63:0] io_ptw_customCSRs_csrs_0_value,
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output [31:0] io_fpu_inst,
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output [63:0] io_fpu_fromint_data,
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output [2:0] io_fpu_fcsr_rm,
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input io_fpu_fcsr_flags_valid,
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input [4:0] io_fpu_fcsr_flags_bits,
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input [63:0] io_fpu_store_data,
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io_fpu_toint_data,
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output io_fpu_ll_resp_val,
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output [2:0] io_fpu_ll_resp_type,
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output [4:0] io_fpu_ll_resp_tag,
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output [63:0] io_fpu_ll_resp_data,
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output io_fpu_valid,
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input io_fpu_fcsr_rdy,
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io_fpu_nack_mem,
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io_fpu_illegal_rm,
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output io_fpu_killx,
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io_fpu_killm,
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input io_fpu_dec_wen,
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io_fpu_dec_ren1,
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io_fpu_dec_ren2,
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io_fpu_dec_ren3,
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io_fpu_sboard_set,
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io_fpu_sboard_clr,
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input [4:0] io_fpu_sboard_clra,
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output io_wfi
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);
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wire io_dmem_req_valid_0;
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wire ll_arb_io_out_ready;
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wire take_pc_wb;
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wire take_pc_mem;
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wire _ll_arb_io_in_0_ready;
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wire _ll_arb_io_out_valid;
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wire [63:0] _ll_arb_io_out_bits_data;
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wire [4:0] _ll_arb_io_out_bits_tag;
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wire _div_io_req_ready;
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wire _div_io_resp_valid;
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wire [63:0] _div_io_resp_bits_data;
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wire [4:0] _div_io_resp_bits_tag;
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wire [63:0] _alu_io_out;
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wire [63:0] _alu_io_adder_out;
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wire _alu_io_cmp_out;
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wire _bpu_io_xcpt_if;
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wire _bpu_io_xcpt_ld;
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wire _bpu_io_xcpt_st;
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wire _bpu_io_debug_if;
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wire _bpu_io_debug_ld;
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wire _bpu_io_debug_st;
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wire [63:0] _csr_io_rw_rdata;
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wire _csr_io_decode_0_fp_illegal;
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wire _csr_io_decode_0_fp_csr;
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wire _csr_io_decode_0_read_illegal;
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wire _csr_io_decode_0_write_illegal;
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wire _csr_io_decode_0_write_flush;
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wire _csr_io_decode_0_system_illegal;
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wire _csr_io_decode_0_virtual_access_illegal;
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wire _csr_io_csr_stall;
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wire _csr_io_eret;
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wire _csr_io_singleStep;
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wire _csr_io_status_debug;
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wire [31:0] _csr_io_status_isa;
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wire _csr_io_status_dv;
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wire _csr_io_status_v;
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wire [33:0] _csr_io_evec;
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wire [63:0] _csr_io_time;
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wire _csr_io_interrupt;
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wire [63:0] _csr_io_interrupt_cause;
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wire _csr_io_bp_0_control_action;
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wire [1:0] _csr_io_bp_0_control_tmatch;
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wire _csr_io_bp_0_control_x;
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wire _csr_io_bp_0_control_w;
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wire _csr_io_bp_0_control_r;
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wire [32:0] _csr_io_bp_0_address;
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wire _csr_io_inhibit_cycle;
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wire _csr_io_trace_0_valid;
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wire [33:0] _csr_io_trace_0_iaddr;
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wire [31:0] _csr_io_trace_0_insn;
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wire _csr_io_trace_0_exception;
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wire [63:0] _csr_io_customCSRs_0_value;
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wire [63:0] _rf_ext_R0_data;
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wire [63:0] _rf_ext_R1_data;
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wire [33:0] _ibuf_io_pc;
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wire _ibuf_io_inst_0_valid;
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wire _ibuf_io_inst_0_bits_xcpt0_pf_inst;
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wire _ibuf_io_inst_0_bits_xcpt0_gf_inst;
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wire _ibuf_io_inst_0_bits_xcpt0_ae_inst;
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wire _ibuf_io_inst_0_bits_xcpt1_pf_inst;
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wire _ibuf_io_inst_0_bits_xcpt1_gf_inst;
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wire _ibuf_io_inst_0_bits_xcpt1_ae_inst;
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wire _ibuf_io_inst_0_bits_replay;
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wire _ibuf_io_inst_0_bits_rvc;
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wire [31:0] _ibuf_io_inst_0_bits_inst_bits;
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wire [4:0] _ibuf_io_inst_0_bits_inst_rd;
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wire [4:0] _ibuf_io_inst_0_bits_inst_rs1;
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wire [4:0] _ibuf_io_inst_0_bits_inst_rs2;
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wire [4:0] _ibuf_io_inst_0_bits_inst_rs3;
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wire [31:0] _ibuf_io_inst_0_bits_raw;
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reg id_reg_pause;
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reg imem_might_request_reg;
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reg ex_ctrl_fp;
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reg ex_ctrl_branch;
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reg ex_ctrl_jal;
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reg ex_ctrl_jalr;
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reg ex_ctrl_rxs2;
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reg ex_ctrl_rxs1;
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reg [2:0] ex_ctrl_sel_alu2;
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reg [1:0] ex_ctrl_sel_alu1;
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reg [2:0] ex_ctrl_sel_imm;
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reg ex_ctrl_alu_dw;
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reg [4:0] ex_ctrl_alu_fn;
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reg ex_ctrl_mem;
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reg [4:0] ex_ctrl_mem_cmd;
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reg ex_ctrl_rfs1;
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reg ex_ctrl_rfs2;
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reg ex_ctrl_wfd;
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reg ex_ctrl_div;
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reg ex_ctrl_wxd;
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reg [2:0] ex_ctrl_csr;
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reg ex_ctrl_fence_i;
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reg mem_ctrl_fp;
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reg mem_ctrl_rocc;
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reg mem_ctrl_branch;
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reg mem_ctrl_jal;
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reg mem_ctrl_jalr;
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reg mem_ctrl_rxs2;
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reg mem_ctrl_rxs1;
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reg mem_ctrl_mem;
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reg mem_ctrl_rfs1;
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reg mem_ctrl_rfs2;
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reg mem_ctrl_wfd;
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reg mem_ctrl_mul;
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reg mem_ctrl_div;
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reg mem_ctrl_wxd;
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reg [2:0] mem_ctrl_csr;
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reg mem_ctrl_fence_i;
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reg mem_ctrl_vec;
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reg wb_ctrl_rocc;
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reg wb_ctrl_rxs2;
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reg wb_ctrl_rxs1;
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reg wb_ctrl_mem;
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reg wb_ctrl_rfs1;
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reg wb_ctrl_rfs2;
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reg wb_ctrl_wfd;
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reg wb_ctrl_div;
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reg wb_ctrl_wxd;
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reg [2:0] wb_ctrl_csr;
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reg wb_ctrl_fence_i;
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reg wb_ctrl_vec;
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reg ex_reg_xcpt_interrupt;
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reg ex_reg_valid;
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reg ex_reg_rvc;
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reg ex_reg_xcpt;
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reg ex_reg_flush_pipe;
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reg ex_reg_load_use;
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reg [63:0] ex_reg_cause;
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reg ex_reg_replay;
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reg [33:0] ex_reg_pc;
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reg [1:0] ex_reg_mem_size;
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reg [31:0] ex_reg_inst;
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reg [31:0] ex_reg_raw_inst;
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reg mem_reg_xcpt_interrupt;
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reg mem_reg_valid;
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reg mem_reg_rvc;
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reg mem_reg_xcpt;
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reg mem_reg_replay;
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reg mem_reg_flush_pipe;
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reg [63:0] mem_reg_cause;
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reg mem_reg_slow_bypass;
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reg mem_reg_load;
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reg mem_reg_store;
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reg [33:0] mem_reg_pc;
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reg [31:0] mem_reg_inst;
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reg mem_reg_hls_or_dv;
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reg [31:0] mem_reg_raw_inst;
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reg [63:0] mem_reg_wdata;
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reg [63:0] mem_reg_rs2;
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reg mem_br_taken;
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reg wb_reg_valid;
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reg wb_reg_xcpt;
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reg wb_reg_replay;
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reg wb_reg_flush_pipe;
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reg [63:0] wb_reg_cause;
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reg [33:0] wb_reg_pc;
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reg wb_reg_hls_or_dv;
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reg [31:0] wb_reg_inst;
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reg [31:0] wb_reg_raw_inst;
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reg [63:0] wb_reg_wdata;
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wire ibuf_io_kill = take_pc_wb | take_pc_mem;
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wire [29:0] id_ctrl_decoder_decoded_invInputs =
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~(_ibuf_io_inst_0_bits_inst_bits[31:2]);
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wire id_ctrl_decoder_decoded_andMatrixOutputs_63_2 =
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&{_ibuf_io_inst_0_bits_inst_bits[0],
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_ibuf_io_inst_0_bits_inst_bits[1],
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id_ctrl_decoder_decoded_invInputs[0],
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id_ctrl_decoder_decoded_invInputs[1],
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id_ctrl_decoder_decoded_invInputs[3],
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id_ctrl_decoder_decoded_invInputs[4],
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id_ctrl_decoder_decoded_invInputs[10]};
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wire id_ctrl_decoder_decoded_andMatrixOutputs_9_2 =
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&{_ibuf_io_inst_0_bits_inst_bits[0],
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_ibuf_io_inst_0_bits_inst_bits[1],
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id_ctrl_decoder_decoded_invInputs[0],
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id_ctrl_decoder_decoded_invInputs[1],
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id_ctrl_decoder_decoded_invInputs[2],
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id_ctrl_decoder_decoded_invInputs[3],
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id_ctrl_decoder_decoded_invInputs[4],
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id_ctrl_decoder_decoded_invInputs[11]};
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wire id_ctrl_decoder_decoded_andMatrixOutputs_0_2 =
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&{_ibuf_io_inst_0_bits_inst_bits[0],
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_ibuf_io_inst_0_bits_inst_bits[1],
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id_ctrl_decoder_decoded_invInputs[0],
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id_ctrl_decoder_decoded_invInputs[1],
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id_ctrl_decoder_decoded_invInputs[2],
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id_ctrl_decoder_decoded_invInputs[4],
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id_ctrl_decoder_decoded_invInputs[12]};
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wire id_ctrl_decoder_decoded_andMatrixOutputs_60_2 =
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&{_ibuf_io_inst_0_bits_inst_bits[0],
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_ibuf_io_inst_0_bits_inst_bits[1],
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id_ctrl_decoder_decoded_invInputs[0],
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_ibuf_io_inst_0_bits_inst_bits[4],
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id_ctrl_decoder_decoded_invInputs[3],
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id_ctrl_decoder_decoded_invInputs[4],
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id_ctrl_decoder_decoded_invInputs[10],
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id_ctrl_decoder_decoded_invInputs[11],
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id_ctrl_decoder_decoded_invInputs[12]};
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wire id_ctrl_decoder_decoded_andMatrixOutputs_27_2 =
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&{_ibuf_io_inst_0_bits_inst_bits[0],
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_ibuf_io_inst_0_bits_inst_bits[1],
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_ibuf_io_inst_0_bits_inst_bits[2],
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id_ctrl_decoder_decoded_invInputs[1],
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_ibuf_io_inst_0_bits_inst_bits[4],
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id_ctrl_decoder_decoded_invInputs[4]};
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wire id_ctrl_decoder_decoded_andMatrixOutputs_82_2 =
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&{_ibuf_io_inst_0_bits_inst_bits[0],
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_ibuf_io_inst_0_bits_inst_bits[1],
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id_ctrl_decoder_decoded_invInputs[0],
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id_ctrl_decoder_decoded_invInputs[1],
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id_ctrl_decoder_decoded_invInputs[2],
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_ibuf_io_inst_0_bits_inst_bits[5],
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id_ctrl_decoder_decoded_invInputs[4],
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id_ctrl_decoder_decoded_invInputs[12]};
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wire id_ctrl_decoder_decoded_andMatrixOutputs_120_2 =
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&{_ibuf_io_inst_0_bits_inst_bits[0],
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_ibuf_io_inst_0_bits_inst_bits[1],
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id_ctrl_decoder_decoded_invInputs[0],
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_ibuf_io_inst_0_bits_inst_bits[4],
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_ibuf_io_inst_0_bits_inst_bits[5],
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id_ctrl_decoder_decoded_invInputs[4],
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id_ctrl_decoder_decoded_invInputs[10],
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id_ctrl_decoder_decoded_invInputs[11],
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id_ctrl_decoder_decoded_invInputs[12],
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id_ctrl_decoder_decoded_invInputs[23],
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id_ctrl_decoder_decoded_invInputs[24],
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id_ctrl_decoder_decoded_invInputs[25],
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id_ctrl_decoder_decoded_invInputs[26],
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id_ctrl_decoder_decoded_invInputs[27],
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id_ctrl_decoder_decoded_invInputs[29]};
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wire id_ctrl_decoder_decoded_andMatrixOutputs_7_2 =
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&{_ibuf_io_inst_0_bits_inst_bits[0],
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_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]};
|
|
wire id_ctrl_decoder_decoded_andMatrixOutputs_62_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
id_ctrl_decoder_decoded_invInputs[10],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]};
|
|
wire id_ctrl_rfs3 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[2],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[6]};
|
|
wire id_ctrl_decoder_decoded_andMatrixOutputs_18_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]};
|
|
wire id_ctrl_decoder_decoded_andMatrixOutputs_84_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
id_ctrl_decoder_decoded_invInputs[2],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[10],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[12]};
|
|
wire id_ctrl_jalr =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[2],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
id_ctrl_decoder_decoded_invInputs[2],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[10],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[12]};
|
|
wire id_ctrl_jal =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[2],
|
|
_ibuf_io_inst_0_bits_inst_bits[3],
|
|
id_ctrl_decoder_decoded_invInputs[2],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
_ibuf_io_inst_0_bits_inst_bits[6]};
|
|
wire id_ctrl_fence_i =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[2],
|
|
_ibuf_io_inst_0_bits_inst_bits[3],
|
|
id_ctrl_decoder_decoded_invInputs[2],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[12],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[12]};
|
|
wire id_ctrl_decoder_decoded_andMatrixOutputs_80_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[12],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]};
|
|
wire id_ctrl_decoder_decoded_andMatrixOutputs_64_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[12],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[23],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]};
|
|
wire id_ctrl_decoder_decoded_andMatrixOutputs_14_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
_ibuf_io_inst_0_bits_inst_bits[12],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[12]};
|
|
wire id_ctrl_decoder_decoded_andMatrixOutputs_118_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
_ibuf_io_inst_0_bits_inst_bits[12]};
|
|
wire id_ctrl_decoder_decoded_andMatrixOutputs_92_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
id_ctrl_decoder_decoded_invInputs[2],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[13],
|
|
id_ctrl_decoder_decoded_invInputs[12]};
|
|
wire id_ctrl_decoder_decoded_andMatrixOutputs_15_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[13]};
|
|
wire id_ctrl_decoder_decoded_andMatrixOutputs_12_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[2],
|
|
_ibuf_io_inst_0_bits_inst_bits[3],
|
|
id_ctrl_decoder_decoded_invInputs[2],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[13],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26]};
|
|
wire id_ctrl_decoder_decoded_andMatrixOutputs_99_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
_ibuf_io_inst_0_bits_inst_bits[13]};
|
|
wire id_ctrl_decoder_decoded_andMatrixOutputs_117_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
_ibuf_io_inst_0_bits_inst_bits[13],
|
|
id_ctrl_decoder_decoded_invInputs[12]};
|
|
wire id_ctrl_decoder_decoded_andMatrixOutputs_102_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
id_ctrl_decoder_decoded_invInputs[2],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
_ibuf_io_inst_0_bits_inst_bits[14]};
|
|
wire id_ctrl_decoder_decoded_andMatrixOutputs_48_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[12],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
_ibuf_io_inst_0_bits_inst_bits[14],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[29]};
|
|
wire id_ctrl_decoder_decoded_andMatrixOutputs_114_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[12],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
_ibuf_io_inst_0_bits_inst_bits[14],
|
|
id_ctrl_decoder_decoded_invInputs[23],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[29]};
|
|
wire id_ctrl_decoder_decoded_andMatrixOutputs_54_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[12],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
_ibuf_io_inst_0_bits_inst_bits[14],
|
|
id_ctrl_decoder_decoded_invInputs[23],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[29]};
|
|
wire id_ctrl_decoder_decoded_andMatrixOutputs_8_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[14],
|
|
_ibuf_io_inst_0_bits_inst_bits[25],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]};
|
|
wire id_ctrl_decoder_decoded_andMatrixOutputs_74_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[2],
|
|
_ibuf_io_inst_0_bits_inst_bits[3],
|
|
id_ctrl_decoder_decoded_invInputs[2],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[13],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
_ibuf_io_inst_0_bits_inst_bits[27],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]};
|
|
wire id_ctrl_decoder_decoded_andMatrixOutputs_88_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[2],
|
|
_ibuf_io_inst_0_bits_inst_bits[3],
|
|
id_ctrl_decoder_decoded_invInputs[2],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
id_ctrl_decoder_decoded_invInputs[18],
|
|
id_ctrl_decoder_decoded_invInputs[19],
|
|
id_ctrl_decoder_decoded_invInputs[20],
|
|
id_ctrl_decoder_decoded_invInputs[21],
|
|
id_ctrl_decoder_decoded_invInputs[22],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
_ibuf_io_inst_0_bits_inst_bits[28],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]};
|
|
wire id_ctrl_decoder_decoded_andMatrixOutputs_45_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[2],
|
|
_ibuf_io_inst_0_bits_inst_bits[3],
|
|
id_ctrl_decoder_decoded_invInputs[2],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[13],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
id_ctrl_decoder_decoded_invInputs[18],
|
|
id_ctrl_decoder_decoded_invInputs[19],
|
|
id_ctrl_decoder_decoded_invInputs[20],
|
|
id_ctrl_decoder_decoded_invInputs[21],
|
|
id_ctrl_decoder_decoded_invInputs[22],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
_ibuf_io_inst_0_bits_inst_bits[28],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]};
|
|
wire id_ctrl_decoder_decoded_andMatrixOutputs_6_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[10],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
_ibuf_io_inst_0_bits_inst_bits[29],
|
|
id_ctrl_decoder_decoded_invInputs[28]};
|
|
wire id_ctrl_decoder_decoded_andMatrixOutputs_86_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
_ibuf_io_inst_0_bits_inst_bits[29],
|
|
id_ctrl_decoder_decoded_invInputs[28]};
|
|
wire id_ctrl_decoder_decoded_andMatrixOutputs_70_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
_ibuf_io_inst_0_bits_inst_bits[29],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]};
|
|
wire id_ctrl_decoder_decoded_andMatrixOutputs_111_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
_ibuf_io_inst_0_bits_inst_bits[20],
|
|
id_ctrl_decoder_decoded_invInputs[19],
|
|
id_ctrl_decoder_decoded_invInputs[20],
|
|
id_ctrl_decoder_decoded_invInputs[21],
|
|
id_ctrl_decoder_decoded_invInputs[22],
|
|
id_ctrl_decoder_decoded_invInputs[23],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
_ibuf_io_inst_0_bits_inst_bits[30]};
|
|
wire id_ctrl_decoder_decoded_andMatrixOutputs_73_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[18],
|
|
id_ctrl_decoder_decoded_invInputs[19],
|
|
id_ctrl_decoder_decoded_invInputs[20],
|
|
id_ctrl_decoder_decoded_invInputs[21],
|
|
id_ctrl_decoder_decoded_invInputs[22],
|
|
_ibuf_io_inst_0_bits_inst_bits[25],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
_ibuf_io_inst_0_bits_inst_bits[30]};
|
|
wire id_ctrl_decoder_decoded_andMatrixOutputs_87_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[18],
|
|
id_ctrl_decoder_decoded_invInputs[19],
|
|
id_ctrl_decoder_decoded_invInputs[20],
|
|
id_ctrl_decoder_decoded_invInputs[21],
|
|
id_ctrl_decoder_decoded_invInputs[22],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
_ibuf_io_inst_0_bits_inst_bits[27],
|
|
_ibuf_io_inst_0_bits_inst_bits[28],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
_ibuf_io_inst_0_bits_inst_bits[30],
|
|
id_ctrl_decoder_decoded_invInputs[29]};
|
|
wire id_ctrl_decoder_decoded_andMatrixOutputs_71_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[20],
|
|
id_ctrl_decoder_decoded_invInputs[21],
|
|
id_ctrl_decoder_decoded_invInputs[22],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
_ibuf_io_inst_0_bits_inst_bits[30],
|
|
_ibuf_io_inst_0_bits_inst_bits[31]};
|
|
wire id_ctrl_decoder_decoded_andMatrixOutputs_65_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[20],
|
|
id_ctrl_decoder_decoded_invInputs[21],
|
|
id_ctrl_decoder_decoded_invInputs[22],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
_ibuf_io_inst_0_bits_inst_bits[30],
|
|
_ibuf_io_inst_0_bits_inst_bits[31]};
|
|
wire id_ctrl_decoder_decoded_andMatrixOutputs_101_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[20],
|
|
id_ctrl_decoder_decoded_invInputs[21],
|
|
id_ctrl_decoder_decoded_invInputs[22],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
_ibuf_io_inst_0_bits_inst_bits[28],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
_ibuf_io_inst_0_bits_inst_bits[30],
|
|
_ibuf_io_inst_0_bits_inst_bits[31]};
|
|
wire id_ctrl_decoder_decoded_andMatrixOutputs_26_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
id_ctrl_decoder_decoded_invInputs[18],
|
|
id_ctrl_decoder_decoded_invInputs[19],
|
|
id_ctrl_decoder_decoded_invInputs[20],
|
|
id_ctrl_decoder_decoded_invInputs[21],
|
|
id_ctrl_decoder_decoded_invInputs[22],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
_ibuf_io_inst_0_bits_inst_bits[29],
|
|
_ibuf_io_inst_0_bits_inst_bits[30],
|
|
_ibuf_io_inst_0_bits_inst_bits[31]};
|
|
wire id_ctrl_decoder_decoded_andMatrixOutputs_46_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[10],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
id_ctrl_decoder_decoded_invInputs[18],
|
|
id_ctrl_decoder_decoded_invInputs[19],
|
|
id_ctrl_decoder_decoded_invInputs[20],
|
|
id_ctrl_decoder_decoded_invInputs[21],
|
|
id_ctrl_decoder_decoded_invInputs[22],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
_ibuf_io_inst_0_bits_inst_bits[28],
|
|
_ibuf_io_inst_0_bits_inst_bits[29],
|
|
_ibuf_io_inst_0_bits_inst_bits[30],
|
|
_ibuf_io_inst_0_bits_inst_bits[31]};
|
|
wire id_ctrl_amo =
|
|
|{id_ctrl_decoder_decoded_andMatrixOutputs_12_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_74_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_88_2};
|
|
wire id_ctrl_wxd =
|
|
|{id_ctrl_decoder_decoded_andMatrixOutputs_63_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_9_2,
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
id_ctrl_decoder_decoded_invInputs[2],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
id_ctrl_decoder_decoded_invInputs[12]},
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_60_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_27_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_120_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_7_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_62_2,
|
|
id_ctrl_jalr,
|
|
id_ctrl_jal,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_80_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_64_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_118_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_15_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_12_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_99_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_48_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_114_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_54_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_8_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_74_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_88_2,
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[10],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
_ibuf_io_inst_0_bits_inst_bits[29],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
_ibuf_io_inst_0_bits_inst_bits[31]},
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
_ibuf_io_inst_0_bits_inst_bits[29],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
_ibuf_io_inst_0_bits_inst_bits[31]},
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_65_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_26_2};
|
|
wire id_ctrl_div =
|
|
|{&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[25],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]},
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
id_ctrl_decoder_decoded_invInputs[10],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
_ibuf_io_inst_0_bits_inst_bits[25],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]},
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_8_2};
|
|
wire id_ctrl_mem =
|
|
|{&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
id_ctrl_decoder_decoded_invInputs[2],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
id_ctrl_decoder_decoded_invInputs[10]},
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_9_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_0_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_92_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_12_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_74_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_45_2};
|
|
wire id_ctrl_rxs1 =
|
|
|{id_ctrl_decoder_decoded_andMatrixOutputs_63_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_9_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_0_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_60_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_120_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_7_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_62_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_84_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_80_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_64_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_14_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_92_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_15_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_12_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_117_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_102_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_48_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_114_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_54_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_8_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_74_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_88_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_101_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_46_2};
|
|
wire id_ctrl_rxs2 =
|
|
|{id_ctrl_decoder_decoded_andMatrixOutputs_82_2,
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
id_ctrl_decoder_decoded_invInputs[2],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[12]},
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_120_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_7_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_62_2,
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
id_ctrl_decoder_decoded_invInputs[23],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]},
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_12_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_102_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_54_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_8_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_74_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_88_2};
|
|
wire id_ctrl_fp =
|
|
|{id_ctrl_rfs3,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_18_2,
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[2],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
id_ctrl_decoder_decoded_invInputs[2],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[13],
|
|
id_ctrl_decoder_decoded_invInputs[12]},
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_6_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_86_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_70_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_111_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_73_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_87_2,
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[18],
|
|
id_ctrl_decoder_decoded_invInputs[19],
|
|
id_ctrl_decoder_decoded_invInputs[20],
|
|
id_ctrl_decoder_decoded_invInputs[21],
|
|
id_ctrl_decoder_decoded_invInputs[22],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
_ibuf_io_inst_0_bits_inst_bits[30],
|
|
_ibuf_io_inst_0_bits_inst_bits[31]},
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_71_2};
|
|
wire [2:0] id_ctrl_csr =
|
|
{|{&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[5],
|
|
id_ctrl_decoder_decoded_invInputs[6],
|
|
id_ctrl_decoder_decoded_invInputs[7],
|
|
id_ctrl_decoder_decoded_invInputs[8],
|
|
id_ctrl_decoder_decoded_invInputs[9],
|
|
id_ctrl_decoder_decoded_invInputs[10],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
id_ctrl_decoder_decoded_invInputs[13],
|
|
id_ctrl_decoder_decoded_invInputs[14],
|
|
id_ctrl_decoder_decoded_invInputs[15],
|
|
id_ctrl_decoder_decoded_invInputs[16],
|
|
id_ctrl_decoder_decoded_invInputs[17],
|
|
id_ctrl_decoder_decoded_invInputs[19],
|
|
id_ctrl_decoder_decoded_invInputs[20],
|
|
id_ctrl_decoder_decoded_invInputs[21],
|
|
id_ctrl_decoder_decoded_invInputs[22],
|
|
id_ctrl_decoder_decoded_invInputs[23],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]},
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_118_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_99_2,
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[5],
|
|
id_ctrl_decoder_decoded_invInputs[6],
|
|
id_ctrl_decoder_decoded_invInputs[7],
|
|
id_ctrl_decoder_decoded_invInputs[8],
|
|
id_ctrl_decoder_decoded_invInputs[9],
|
|
id_ctrl_decoder_decoded_invInputs[10],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
id_ctrl_decoder_decoded_invInputs[13],
|
|
id_ctrl_decoder_decoded_invInputs[14],
|
|
id_ctrl_decoder_decoded_invInputs[15],
|
|
id_ctrl_decoder_decoded_invInputs[16],
|
|
id_ctrl_decoder_decoded_invInputs[17],
|
|
_ibuf_io_inst_0_bits_inst_bits[20],
|
|
id_ctrl_decoder_decoded_invInputs[19],
|
|
_ibuf_io_inst_0_bits_inst_bits[22],
|
|
id_ctrl_decoder_decoded_invInputs[21],
|
|
id_ctrl_decoder_decoded_invInputs[22],
|
|
id_ctrl_decoder_decoded_invInputs[23],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
_ibuf_io_inst_0_bits_inst_bits[28],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]},
|
|
&{_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[5],
|
|
id_ctrl_decoder_decoded_invInputs[6],
|
|
id_ctrl_decoder_decoded_invInputs[7],
|
|
id_ctrl_decoder_decoded_invInputs[8],
|
|
id_ctrl_decoder_decoded_invInputs[9],
|
|
id_ctrl_decoder_decoded_invInputs[10],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
id_ctrl_decoder_decoded_invInputs[13],
|
|
id_ctrl_decoder_decoded_invInputs[14],
|
|
id_ctrl_decoder_decoded_invInputs[15],
|
|
id_ctrl_decoder_decoded_invInputs[16],
|
|
id_ctrl_decoder_decoded_invInputs[17],
|
|
id_ctrl_decoder_decoded_invInputs[18],
|
|
_ibuf_io_inst_0_bits_inst_bits[21],
|
|
id_ctrl_decoder_decoded_invInputs[20],
|
|
id_ctrl_decoder_decoded_invInputs[21],
|
|
id_ctrl_decoder_decoded_invInputs[22],
|
|
id_ctrl_decoder_decoded_invInputs[23],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
_ibuf_io_inst_0_bits_inst_bits[28],
|
|
_ibuf_io_inst_0_bits_inst_bits[29],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]},
|
|
&{_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[5],
|
|
id_ctrl_decoder_decoded_invInputs[6],
|
|
id_ctrl_decoder_decoded_invInputs[7],
|
|
id_ctrl_decoder_decoded_invInputs[8],
|
|
id_ctrl_decoder_decoded_invInputs[9],
|
|
id_ctrl_decoder_decoded_invInputs[10],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
id_ctrl_decoder_decoded_invInputs[13],
|
|
id_ctrl_decoder_decoded_invInputs[14],
|
|
id_ctrl_decoder_decoded_invInputs[15],
|
|
id_ctrl_decoder_decoded_invInputs[16],
|
|
id_ctrl_decoder_decoded_invInputs[17],
|
|
id_ctrl_decoder_decoded_invInputs[18],
|
|
_ibuf_io_inst_0_bits_inst_bits[21],
|
|
id_ctrl_decoder_decoded_invInputs[20],
|
|
id_ctrl_decoder_decoded_invInputs[21],
|
|
_ibuf_io_inst_0_bits_inst_bits[24],
|
|
_ibuf_io_inst_0_bits_inst_bits[25],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
_ibuf_io_inst_0_bits_inst_bits[27],
|
|
_ibuf_io_inst_0_bits_inst_bits[28],
|
|
_ibuf_io_inst_0_bits_inst_bits[29],
|
|
_ibuf_io_inst_0_bits_inst_bits[30],
|
|
id_ctrl_decoder_decoded_invInputs[29]}},
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_99_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_118_2};
|
|
reg id_reg_fence;
|
|
wire _id_csr_ren_T = id_ctrl_csr == 3'h6;
|
|
wire _id_csr_ren_T_1 = &id_ctrl_csr;
|
|
wire id_csr_en = _id_csr_ren_T | _id_csr_ren_T_1 | id_ctrl_csr == 3'h5;
|
|
wire id_mem_busy = ~io_dmem_ordered | io_dmem_req_valid_0;
|
|
wire bypass_sources_3_1 = mem_reg_valid & mem_ctrl_wxd;
|
|
wire _fp_data_hazard_ex_T_1 =
|
|
ex_reg_inst[11:7] == _ibuf_io_inst_0_bits_inst_rs1;
|
|
wire _fp_data_hazard_mem_T_1 =
|
|
mem_reg_inst[11:7] == _ibuf_io_inst_0_bits_inst_rs1;
|
|
wire _fp_data_hazard_ex_T_3 =
|
|
ex_reg_inst[11:7] == _ibuf_io_inst_0_bits_inst_rs2;
|
|
wire _fp_data_hazard_mem_T_3 =
|
|
mem_reg_inst[11:7] == _ibuf_io_inst_0_bits_inst_rs2;
|
|
reg ex_reg_rs_bypass_0;
|
|
reg ex_reg_rs_bypass_1;
|
|
reg [1:0] ex_reg_rs_lsb_0;
|
|
reg [1:0] ex_reg_rs_lsb_1;
|
|
reg [61:0] ex_reg_rs_msb_0;
|
|
reg [61:0] ex_reg_rs_msb_1;
|
|
wire [3:0][63:0] _GEN =
|
|
{{io_dmem_resp_bits_data_word_bypass}, {wb_reg_wdata}, {mem_reg_wdata}, {64'h0}};
|
|
wire [63:0] ex_rs_0 =
|
|
ex_reg_rs_bypass_0 ? _GEN[ex_reg_rs_lsb_0] : {ex_reg_rs_msb_0, ex_reg_rs_lsb_0};
|
|
wire [63:0] ex_rs_1 =
|
|
ex_reg_rs_bypass_1 ? _GEN[ex_reg_rs_lsb_1] : {ex_reg_rs_msb_1, ex_reg_rs_lsb_1};
|
|
wire _ex_imm_b0_T_4 = ex_ctrl_sel_imm == 3'h5;
|
|
wire ex_imm_sign = ~_ex_imm_b0_T_4 & ex_reg_inst[31];
|
|
wire _ex_imm_b4_1_T = ex_ctrl_sel_imm == 3'h2;
|
|
wire _ex_imm_b4_1_T_2 = ex_ctrl_sel_imm == 3'h1;
|
|
wire _ex_imm_b0_T = ex_ctrl_sel_imm == 3'h0;
|
|
wire [3:0][63:0] _GEN_0 =
|
|
{{64'h0}, {{{30{ex_reg_pc[33]}}, ex_reg_pc}}, {ex_rs_0}, {64'h0}};
|
|
wire [3:0] _ex_op2_T_1 = ex_reg_rvc ? 4'h2 : 4'h4;
|
|
wire div_io_req_valid = ex_reg_valid & ex_ctrl_div;
|
|
wire ex_pc_valid = ex_reg_valid | ex_reg_replay | ex_reg_xcpt_interrupt;
|
|
wire wb_dcache_miss = wb_ctrl_mem & ~io_dmem_resp_valid;
|
|
wire replay_ex =
|
|
ex_reg_replay | ex_reg_valid
|
|
& (ex_ctrl_mem & ~io_dmem_req_ready | ex_ctrl_div & ~_div_io_req_ready
|
|
| wb_dcache_miss & ex_reg_load_use);
|
|
wire ctrl_killx = ibuf_io_kill | replay_ex | ~ex_reg_valid;
|
|
wire _mem_cfi_taken_T = mem_ctrl_branch & mem_br_taken;
|
|
wire [3:0] _mem_br_target_T_6 = mem_reg_rvc ? 4'h2 : 4'h4;
|
|
wire [31:0] _mem_br_target_T_8 =
|
|
_mem_cfi_taken_T
|
|
? {{20{mem_reg_inst[31]}},
|
|
mem_reg_inst[7],
|
|
mem_reg_inst[30:25],
|
|
mem_reg_inst[11:8],
|
|
1'h0}
|
|
: mem_ctrl_jal
|
|
? {{12{mem_reg_inst[31]}},
|
|
mem_reg_inst[19:12],
|
|
mem_reg_inst[20],
|
|
mem_reg_inst[30:21],
|
|
1'h0}
|
|
: {{28{_mem_br_target_T_6[3]}}, _mem_br_target_T_6};
|
|
wire [33:0] _mem_br_target_T_9 =
|
|
mem_reg_pc + {{2{_mem_br_target_T_8[31]}}, _mem_br_target_T_8};
|
|
wire [32:0] _mem_npc_T_4 =
|
|
mem_ctrl_jalr
|
|
? {mem_reg_wdata[63:33] == 31'h0 | (&(mem_reg_wdata[63:33]))
|
|
? mem_reg_wdata[33]
|
|
: ~(mem_reg_wdata[32]),
|
|
mem_reg_wdata[32:1]}
|
|
: _mem_br_target_T_9[33:1];
|
|
wire [33:0] mem_npc = {_mem_npc_T_4, 1'h0};
|
|
wire mem_cfi_taken = _mem_cfi_taken_T | mem_ctrl_jalr | mem_ctrl_jal;
|
|
assign take_pc_mem = mem_reg_valid & ~mem_reg_xcpt & mem_cfi_taken;
|
|
wire mem_debug_breakpoint =
|
|
mem_reg_load & _bpu_io_debug_ld | mem_reg_store & _bpu_io_debug_st;
|
|
wire mem_ldst_xcpt =
|
|
mem_debug_breakpoint | mem_reg_load & _bpu_io_xcpt_ld | mem_reg_store
|
|
& _bpu_io_xcpt_st;
|
|
wire dcache_kill_mem = bypass_sources_3_1 & io_dmem_replay_next;
|
|
wire fpu_kill_mem = mem_reg_valid & mem_ctrl_fp & io_fpu_nack_mem;
|
|
wire killm_common =
|
|
dcache_kill_mem | take_pc_wb | mem_reg_xcpt | ~mem_reg_valid;
|
|
reg div_io_kill_REG;
|
|
wire _GEN_1 = wb_reg_valid & wb_ctrl_mem;
|
|
wire _GEN_2 = _GEN_1 & io_dmem_s2_xcpt_pf_st;
|
|
wire _GEN_3 = _GEN_1 & io_dmem_s2_xcpt_pf_ld;
|
|
wire _GEN_4 = _GEN_1 & io_dmem_s2_xcpt_ae_st;
|
|
wire _GEN_5 = _GEN_1 & io_dmem_s2_xcpt_ae_ld;
|
|
wire _GEN_6 = _GEN_1 & io_dmem_s2_xcpt_ma_st;
|
|
wire wb_xcpt =
|
|
wb_reg_xcpt | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6 | _GEN_1
|
|
& io_dmem_s2_xcpt_ma_ld;
|
|
wire wb_wxd = wb_reg_valid & wb_ctrl_wxd;
|
|
wire wb_set_sboard =
|
|
wb_ctrl_div | wb_dcache_miss | wb_ctrl_rocc | wb_ctrl_vec;
|
|
wire _replay_wb_T =
|
|
io_dmem_s2_nack | wb_reg_replay | wb_reg_valid & wb_ctrl_rocc;
|
|
assign take_pc_wb = _replay_wb_T | wb_xcpt | _csr_io_eret | wb_reg_flush_pipe;
|
|
wire dmem_resp_valid = io_dmem_resp_valid & io_dmem_resp_bits_has_data;
|
|
wire dmem_resp_replay = dmem_resp_valid & io_dmem_resp_bits_replay;
|
|
wire _GEN_7 = dmem_resp_replay & ~(io_dmem_resp_bits_tag[0]);
|
|
assign ll_arb_io_out_ready = ~_GEN_7 & ~wb_wxd;
|
|
wire [4:0] ll_waddr =
|
|
_GEN_7 ? io_dmem_resp_bits_tag[5:1] : _ll_arb_io_out_bits_tag;
|
|
wire ll_wen = _GEN_7 | ll_arb_io_out_ready & _ll_arb_io_out_valid;
|
|
wire wb_valid = wb_reg_valid & ~_replay_wb_T & ~wb_xcpt;
|
|
wire wb_wen = wb_valid & wb_ctrl_wxd;
|
|
wire rf_wen = wb_wen | ll_wen;
|
|
wire [4:0] rf_waddr = ll_wen ? ll_waddr : wb_reg_inst[11:7];
|
|
wire [63:0] rf_wdata =
|
|
dmem_resp_valid & ~(io_dmem_resp_bits_tag[0])
|
|
? io_dmem_resp_bits_data
|
|
: ll_wen
|
|
? _ll_arb_io_out_bits_data
|
|
: (|wb_ctrl_csr) ? _csr_io_rw_rdata : wb_reg_wdata;
|
|
wire _GEN_8 = |rf_waddr;
|
|
wire [63:0] id_rs_0 =
|
|
rf_wen & _GEN_8 & rf_waddr == _ibuf_io_inst_0_bits_inst_rs1
|
|
? rf_wdata
|
|
: _rf_ext_R1_data;
|
|
wire [63:0] id_rs_1 =
|
|
rf_wen & _GEN_8 & rf_waddr == _ibuf_io_inst_0_bits_inst_rs2
|
|
? rf_wdata
|
|
: _rf_ext_R0_data;
|
|
wire _htval_valid_imem_T = wb_reg_cause == 64'h14;
|
|
wire tval_any_addr =
|
|
~wb_reg_xcpt | wb_reg_cause == 64'h3 | wb_reg_cause == 64'h1 | wb_reg_cause == 64'hC
|
|
| _htval_valid_imem_T;
|
|
wire htval_valid_imem = wb_reg_xcpt & _htval_valid_imem_T;
|
|
wire hazard_targets_0_1 = id_ctrl_rxs1 & (|_ibuf_io_inst_0_bits_inst_rs1);
|
|
wire hazard_targets_1_1 = id_ctrl_rxs2 & (|_ibuf_io_inst_0_bits_inst_rs2);
|
|
wire hazard_targets_2_1 = id_ctrl_wxd & (|_ibuf_io_inst_0_bits_inst_rd);
|
|
reg [31:0] _r;
|
|
wire [31:0] r = {_r[31:1], 1'h0};
|
|
wire [31:0] _GEN_9 = {27'h0, _ibuf_io_inst_0_bits_inst_rs1};
|
|
wire [31:0] _id_sboard_hazard_T = r >> _GEN_9;
|
|
wire [31:0] _GEN_10 = {27'h0, _ibuf_io_inst_0_bits_inst_rs2};
|
|
wire [31:0] _id_sboard_hazard_T_7 = r >> _GEN_10;
|
|
wire [31:0] _GEN_11 = {27'h0, _ibuf_io_inst_0_bits_inst_rd};
|
|
wire [31:0] _id_sboard_hazard_T_14 = r >> _GEN_11;
|
|
wire _fp_data_hazard_ex_T_7 =
|
|
_ibuf_io_inst_0_bits_inst_rd == ex_reg_inst[11:7];
|
|
wire _fp_data_hazard_mem_T_7 =
|
|
_ibuf_io_inst_0_bits_inst_rd == mem_reg_inst[11:7];
|
|
wire data_hazard_mem =
|
|
mem_ctrl_wxd
|
|
& (hazard_targets_0_1 & _fp_data_hazard_mem_T_1 | hazard_targets_1_1
|
|
& _fp_data_hazard_mem_T_3 | hazard_targets_2_1 & _fp_data_hazard_mem_T_7);
|
|
wire _fp_data_hazard_wb_T_1 =
|
|
_ibuf_io_inst_0_bits_inst_rs1 == wb_reg_inst[11:7];
|
|
wire _fp_data_hazard_wb_T_3 =
|
|
_ibuf_io_inst_0_bits_inst_rs2 == wb_reg_inst[11:7];
|
|
wire _fp_data_hazard_wb_T_7 =
|
|
_ibuf_io_inst_0_bits_inst_rd == wb_reg_inst[11:7];
|
|
reg [31:0] _id_stall_fpu_r;
|
|
wire [31:0] _id_stall_fpu_T_20 = _id_stall_fpu_r >> _GEN_9;
|
|
wire [31:0] _id_stall_fpu_T_23 = _id_stall_fpu_r >> _GEN_10;
|
|
wire [31:0] _id_stall_fpu_T_26 = _id_stall_fpu_r >> _ibuf_io_inst_0_bits_inst_rs3;
|
|
wire [31:0] _id_stall_fpu_T_29 = _id_stall_fpu_r >> _GEN_11;
|
|
reg dcache_blocked_blocked;
|
|
wire _ctrl_stalld_T_32 =
|
|
ex_reg_valid
|
|
& (ex_ctrl_wxd
|
|
& (hazard_targets_0_1 & _fp_data_hazard_ex_T_1 | hazard_targets_1_1
|
|
& _fp_data_hazard_ex_T_3 | hazard_targets_2_1 & _fp_data_hazard_ex_T_7)
|
|
& ((|ex_ctrl_csr) | ex_ctrl_jalr | ex_ctrl_mem | ex_ctrl_div | ex_ctrl_fp)
|
|
| id_ctrl_fp & ex_ctrl_wfd
|
|
& (io_fpu_dec_ren1 & _fp_data_hazard_ex_T_1 | io_fpu_dec_ren2
|
|
& _fp_data_hazard_ex_T_3 | io_fpu_dec_ren3
|
|
& _ibuf_io_inst_0_bits_inst_rs3 == ex_reg_inst[11:7] | io_fpu_dec_wen
|
|
& _fp_data_hazard_ex_T_7)) | mem_reg_valid
|
|
& (data_hazard_mem
|
|
& ((|mem_ctrl_csr) | mem_ctrl_mem & mem_reg_slow_bypass | mem_ctrl_mul
|
|
| mem_ctrl_div | mem_ctrl_fp | mem_ctrl_rocc | mem_ctrl_vec) | id_ctrl_fp
|
|
& mem_ctrl_wfd
|
|
& (io_fpu_dec_ren1 & _fp_data_hazard_mem_T_1 | io_fpu_dec_ren2
|
|
& _fp_data_hazard_mem_T_3 | io_fpu_dec_ren3
|
|
& _ibuf_io_inst_0_bits_inst_rs3 == mem_reg_inst[11:7] | io_fpu_dec_wen
|
|
& _fp_data_hazard_mem_T_7)) | wb_reg_valid
|
|
& (wb_ctrl_wxd
|
|
& (hazard_targets_0_1 & _fp_data_hazard_wb_T_1 | hazard_targets_1_1
|
|
& _fp_data_hazard_wb_T_3 | hazard_targets_2_1 & _fp_data_hazard_wb_T_7)
|
|
& wb_set_sboard | id_ctrl_fp & wb_ctrl_wfd
|
|
& (io_fpu_dec_ren1 & _fp_data_hazard_wb_T_1 | io_fpu_dec_ren2
|
|
& _fp_data_hazard_wb_T_3 | io_fpu_dec_ren3
|
|
& _ibuf_io_inst_0_bits_inst_rs3 == wb_reg_inst[11:7] | io_fpu_dec_wen
|
|
& _fp_data_hazard_wb_T_7)) | hazard_targets_0_1 & _id_sboard_hazard_T[0]
|
|
& ~(ll_wen & ll_waddr == _ibuf_io_inst_0_bits_inst_rs1) | hazard_targets_1_1
|
|
& _id_sboard_hazard_T_7[0] & ~(ll_wen & ll_waddr == _ibuf_io_inst_0_bits_inst_rs2)
|
|
| hazard_targets_2_1 & _id_sboard_hazard_T_14[0]
|
|
& ~(ll_wen & ll_waddr == _ibuf_io_inst_0_bits_inst_rd) | _csr_io_singleStep
|
|
& (ex_reg_valid | mem_reg_valid | wb_reg_valid) | id_csr_en & _csr_io_decode_0_fp_csr
|
|
& ~io_fpu_fcsr_rdy | id_ctrl_fp
|
|
& (io_fpu_dec_ren1 & _id_stall_fpu_T_20[0] | io_fpu_dec_ren2 & _id_stall_fpu_T_23[0]
|
|
| io_fpu_dec_ren3 & _id_stall_fpu_T_26[0] | io_fpu_dec_wen & _id_stall_fpu_T_29[0])
|
|
| id_ctrl_mem & dcache_blocked_blocked & ~io_dmem_perf_grant | id_ctrl_div
|
|
& (~(_div_io_req_ready | _div_io_resp_valid & ~wb_wxd) | div_io_req_valid)
|
|
| id_mem_busy
|
|
& (id_ctrl_amo & _ibuf_io_inst_0_bits_inst_bits[25] | id_ctrl_fence_i | id_reg_fence
|
|
& id_ctrl_mem) | _csr_io_csr_stall | id_reg_pause;
|
|
wire ctrl_killd =
|
|
~_ibuf_io_inst_0_valid | _ibuf_io_inst_0_bits_replay | ibuf_io_kill
|
|
| _ctrl_stalld_T_32 | _csr_io_interrupt;
|
|
assign io_dmem_req_valid_0 = ex_reg_valid & ex_ctrl_mem;
|
|
reg [63:0] coreMonitorBundle_rd0val_REG;
|
|
reg [63:0] coreMonitorBundle_rd0val_REG_1;
|
|
reg [63:0] coreMonitorBundle_rd1val_REG;
|
|
reg [63:0] coreMonitorBundle_rd1val_REG_1;
|
|
`ifndef SYNTHESIS
|
|
always @(posedge clock) begin
|
|
if ((`PRINTF_COND_) & ~reset & htval_valid_imem)
|
|
$fwrite(32'h80000002,
|
|
"Assertion failed\n at RocketCore.scala:885 assert(!htval_valid_imem || io.imem.gpa.valid)\n");
|
|
if ((`PRINTF_COND_) & _csr_io_trace_0_valid & ~reset) begin
|
|
automatic logic coreMonitorBundle_wrenx = wb_wen & ~wb_set_sboard;
|
|
automatic logic _GEN_12 = wb_ctrl_rxs1 | wb_ctrl_rfs1;
|
|
automatic logic _GEN_13 = wb_ctrl_rxs2 | wb_ctrl_rfs2;
|
|
$fwrite(32'h80000002,
|
|
"C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",
|
|
1'h0, _csr_io_time[31:0],
|
|
_csr_io_trace_0_valid & ~_csr_io_trace_0_exception,
|
|
{{30{_csr_io_trace_0_iaddr[33]}}, _csr_io_trace_0_iaddr},
|
|
wb_ctrl_wxd | wb_ctrl_wfd ? wb_reg_inst[11:7] : 5'h0,
|
|
coreMonitorBundle_wrenx ? rf_wdata : 64'h0, coreMonitorBundle_wrenx,
|
|
_GEN_12 ? wb_reg_inst[19:15] : 5'h0,
|
|
_GEN_12 ? coreMonitorBundle_rd0val_REG_1 : 64'h0,
|
|
_GEN_13 ? wb_reg_inst[24:20] : 5'h0,
|
|
_GEN_13 ? coreMonitorBundle_rd1val_REG_1 : 64'h0, _csr_io_trace_0_insn,
|
|
_csr_io_trace_0_insn);
|
|
end
|
|
end // always @(posedge)
|
|
`endif // not def SYNTHESIS
|
|
always @(posedge clock) begin
|
|
automatic logic id_ctrl_fence;
|
|
automatic logic id_ctrl_decoder_decoded_andMatrixOutputs_59_2;
|
|
automatic logic id_ctrl_decoder_decoded_andMatrixOutputs_23_2;
|
|
automatic logic id_ctrl_legal;
|
|
automatic logic _GEN_14;
|
|
automatic logic id_bypass_src_1_0;
|
|
automatic logic id_system_insn;
|
|
automatic logic id_csr_ren;
|
|
automatic logic id_illegal_insn;
|
|
automatic logic id_virtual_insn;
|
|
automatic logic id_xcpt;
|
|
automatic logic bypass_sources_1_1;
|
|
automatic logic bypass_sources_2_1;
|
|
automatic logic id_bypass_src_1_1;
|
|
automatic logic id_bypass_src_1_2;
|
|
automatic logic do_bypass_1;
|
|
automatic logic _GEN_15;
|
|
automatic logic mem_pc_valid =
|
|
mem_reg_valid | mem_reg_replay | mem_reg_xcpt_interrupt;
|
|
automatic logic _mem_npc_misaligned_T_3;
|
|
automatic logic _GEN_16 = mem_reg_valid & mem_reg_flush_pipe;
|
|
automatic logic _GEN_17 = _GEN_16 | ~ex_pc_valid;
|
|
automatic logic _GEN_18;
|
|
automatic logic _GEN_19;
|
|
automatic logic _GEN_20;
|
|
automatic logic mem_xcpt;
|
|
automatic logic ctrl_killm;
|
|
id_ctrl_fence =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[2],
|
|
_ibuf_io_inst_0_bits_inst_bits[3],
|
|
id_ctrl_decoder_decoded_invInputs[2],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[12]};
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_59_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
_ibuf_io_inst_0_bits_inst_bits[12],
|
|
id_ctrl_decoder_decoded_invInputs[11]};
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_23_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
_ibuf_io_inst_0_bits_inst_bits[20],
|
|
id_ctrl_decoder_decoded_invInputs[19],
|
|
id_ctrl_decoder_decoded_invInputs[20],
|
|
id_ctrl_decoder_decoded_invInputs[21],
|
|
id_ctrl_decoder_decoded_invInputs[22],
|
|
id_ctrl_decoder_decoded_invInputs[23],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
_ibuf_io_inst_0_bits_inst_bits[30],
|
|
id_ctrl_decoder_decoded_invInputs[29]};
|
|
id_ctrl_legal =
|
|
|{id_ctrl_decoder_decoded_andMatrixOutputs_63_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_9_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_0_2,
|
|
id_ctrl_fence,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_60_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_27_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_120_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_7_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_62_2,
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[2],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[24]},
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_18_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_84_2,
|
|
id_ctrl_jal,
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[5],
|
|
id_ctrl_decoder_decoded_invInputs[6],
|
|
id_ctrl_decoder_decoded_invInputs[7],
|
|
id_ctrl_decoder_decoded_invInputs[8],
|
|
id_ctrl_decoder_decoded_invInputs[9],
|
|
id_ctrl_decoder_decoded_invInputs[10],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
id_ctrl_decoder_decoded_invInputs[13],
|
|
id_ctrl_decoder_decoded_invInputs[14],
|
|
id_ctrl_decoder_decoded_invInputs[15],
|
|
id_ctrl_decoder_decoded_invInputs[16],
|
|
id_ctrl_decoder_decoded_invInputs[17],
|
|
id_ctrl_decoder_decoded_invInputs[19],
|
|
id_ctrl_decoder_decoded_invInputs[20],
|
|
id_ctrl_decoder_decoded_invInputs[21],
|
|
id_ctrl_decoder_decoded_invInputs[22],
|
|
id_ctrl_decoder_decoded_invInputs[23],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]},
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_80_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_64_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_59_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_92_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_15_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_12_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_99_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_102_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_48_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_114_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_54_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_8_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_74_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_45_2,
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[5],
|
|
id_ctrl_decoder_decoded_invInputs[6],
|
|
id_ctrl_decoder_decoded_invInputs[7],
|
|
id_ctrl_decoder_decoded_invInputs[8],
|
|
id_ctrl_decoder_decoded_invInputs[9],
|
|
id_ctrl_decoder_decoded_invInputs[10],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
id_ctrl_decoder_decoded_invInputs[13],
|
|
id_ctrl_decoder_decoded_invInputs[14],
|
|
id_ctrl_decoder_decoded_invInputs[15],
|
|
id_ctrl_decoder_decoded_invInputs[16],
|
|
id_ctrl_decoder_decoded_invInputs[17],
|
|
_ibuf_io_inst_0_bits_inst_bits[20],
|
|
id_ctrl_decoder_decoded_invInputs[19],
|
|
_ibuf_io_inst_0_bits_inst_bits[22],
|
|
id_ctrl_decoder_decoded_invInputs[21],
|
|
id_ctrl_decoder_decoded_invInputs[22],
|
|
id_ctrl_decoder_decoded_invInputs[23],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
_ibuf_io_inst_0_bits_inst_bits[28],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]},
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_6_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_86_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_70_2,
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[5],
|
|
id_ctrl_decoder_decoded_invInputs[6],
|
|
id_ctrl_decoder_decoded_invInputs[7],
|
|
id_ctrl_decoder_decoded_invInputs[8],
|
|
id_ctrl_decoder_decoded_invInputs[9],
|
|
id_ctrl_decoder_decoded_invInputs[10],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
id_ctrl_decoder_decoded_invInputs[13],
|
|
id_ctrl_decoder_decoded_invInputs[14],
|
|
id_ctrl_decoder_decoded_invInputs[15],
|
|
id_ctrl_decoder_decoded_invInputs[16],
|
|
id_ctrl_decoder_decoded_invInputs[17],
|
|
id_ctrl_decoder_decoded_invInputs[18],
|
|
_ibuf_io_inst_0_bits_inst_bits[21],
|
|
id_ctrl_decoder_decoded_invInputs[20],
|
|
id_ctrl_decoder_decoded_invInputs[21],
|
|
id_ctrl_decoder_decoded_invInputs[22],
|
|
id_ctrl_decoder_decoded_invInputs[23],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
_ibuf_io_inst_0_bits_inst_bits[28],
|
|
_ibuf_io_inst_0_bits_inst_bits[29],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]},
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_111_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_73_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_87_2,
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[5],
|
|
id_ctrl_decoder_decoded_invInputs[6],
|
|
id_ctrl_decoder_decoded_invInputs[7],
|
|
id_ctrl_decoder_decoded_invInputs[8],
|
|
id_ctrl_decoder_decoded_invInputs[9],
|
|
id_ctrl_decoder_decoded_invInputs[10],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
id_ctrl_decoder_decoded_invInputs[13],
|
|
id_ctrl_decoder_decoded_invInputs[14],
|
|
id_ctrl_decoder_decoded_invInputs[15],
|
|
id_ctrl_decoder_decoded_invInputs[16],
|
|
id_ctrl_decoder_decoded_invInputs[17],
|
|
id_ctrl_decoder_decoded_invInputs[18],
|
|
_ibuf_io_inst_0_bits_inst_bits[21],
|
|
id_ctrl_decoder_decoded_invInputs[20],
|
|
id_ctrl_decoder_decoded_invInputs[21],
|
|
_ibuf_io_inst_0_bits_inst_bits[24],
|
|
_ibuf_io_inst_0_bits_inst_bits[25],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
_ibuf_io_inst_0_bits_inst_bits[27],
|
|
_ibuf_io_inst_0_bits_inst_bits[28],
|
|
_ibuf_io_inst_0_bits_inst_bits[29],
|
|
_ibuf_io_inst_0_bits_inst_bits[30],
|
|
id_ctrl_decoder_decoded_invInputs[29]},
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_71_2,
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[10],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
id_ctrl_decoder_decoded_invInputs[18],
|
|
id_ctrl_decoder_decoded_invInputs[19],
|
|
id_ctrl_decoder_decoded_invInputs[20],
|
|
id_ctrl_decoder_decoded_invInputs[21],
|
|
id_ctrl_decoder_decoded_invInputs[22],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
_ibuf_io_inst_0_bits_inst_bits[29],
|
|
_ibuf_io_inst_0_bits_inst_bits[30],
|
|
_ibuf_io_inst_0_bits_inst_bits[31]},
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_26_2};
|
|
_GEN_14 = |_ibuf_io_inst_0_bits_inst_rs1;
|
|
id_bypass_src_1_0 = _ibuf_io_inst_0_bits_inst_rs2 == 5'h0;
|
|
id_system_insn = id_ctrl_csr == 3'h4;
|
|
id_csr_ren = (_id_csr_ren_T | _id_csr_ren_T_1) & ~_GEN_14;
|
|
id_illegal_insn =
|
|
~id_ctrl_legal | id_ctrl_div & ~(_csr_io_status_isa[12]) | id_ctrl_amo
|
|
& ~(_csr_io_status_isa[0]) | id_ctrl_fp
|
|
& (_csr_io_decode_0_fp_illegal | io_fpu_illegal_rm)
|
|
| (|{&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[2],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
id_ctrl_decoder_decoded_invInputs[2],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[12],
|
|
_ibuf_io_inst_0_bits_inst_bits[13],
|
|
id_ctrl_decoder_decoded_invInputs[12]},
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[2],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
_ibuf_io_inst_0_bits_inst_bits[25],
|
|
id_ctrl_decoder_decoded_invInputs[24]},
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
_ibuf_io_inst_0_bits_inst_bits[25],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]},
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[10],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
_ibuf_io_inst_0_bits_inst_bits[25],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
_ibuf_io_inst_0_bits_inst_bits[29],
|
|
id_ctrl_decoder_decoded_invInputs[28]},
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
_ibuf_io_inst_0_bits_inst_bits[25],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
_ibuf_io_inst_0_bits_inst_bits[29],
|
|
id_ctrl_decoder_decoded_invInputs[28]},
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
_ibuf_io_inst_0_bits_inst_bits[25],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
_ibuf_io_inst_0_bits_inst_bits[29],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]},
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_23_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_73_2,
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[18],
|
|
id_ctrl_decoder_decoded_invInputs[19],
|
|
id_ctrl_decoder_decoded_invInputs[20],
|
|
id_ctrl_decoder_decoded_invInputs[21],
|
|
id_ctrl_decoder_decoded_invInputs[22],
|
|
_ibuf_io_inst_0_bits_inst_bits[25],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
_ibuf_io_inst_0_bits_inst_bits[27],
|
|
_ibuf_io_inst_0_bits_inst_bits[28],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
_ibuf_io_inst_0_bits_inst_bits[30],
|
|
id_ctrl_decoder_decoded_invInputs[29]},
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[20],
|
|
id_ctrl_decoder_decoded_invInputs[21],
|
|
id_ctrl_decoder_decoded_invInputs[22],
|
|
_ibuf_io_inst_0_bits_inst_bits[25],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
_ibuf_io_inst_0_bits_inst_bits[30],
|
|
_ibuf_io_inst_0_bits_inst_bits[31]},
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[10],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
id_ctrl_decoder_decoded_invInputs[18],
|
|
id_ctrl_decoder_decoded_invInputs[19],
|
|
id_ctrl_decoder_decoded_invInputs[20],
|
|
id_ctrl_decoder_decoded_invInputs[21],
|
|
id_ctrl_decoder_decoded_invInputs[22],
|
|
_ibuf_io_inst_0_bits_inst_bits[25],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
_ibuf_io_inst_0_bits_inst_bits[29],
|
|
_ibuf_io_inst_0_bits_inst_bits[30],
|
|
_ibuf_io_inst_0_bits_inst_bits[31]},
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
id_ctrl_decoder_decoded_invInputs[18],
|
|
id_ctrl_decoder_decoded_invInputs[19],
|
|
id_ctrl_decoder_decoded_invInputs[20],
|
|
id_ctrl_decoder_decoded_invInputs[21],
|
|
id_ctrl_decoder_decoded_invInputs[22],
|
|
_ibuf_io_inst_0_bits_inst_bits[25],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
_ibuf_io_inst_0_bits_inst_bits[29],
|
|
_ibuf_io_inst_0_bits_inst_bits[30],
|
|
_ibuf_io_inst_0_bits_inst_bits[31]}}) & ~(_csr_io_status_isa[3])
|
|
| _ibuf_io_inst_0_bits_rvc & ~(_csr_io_status_isa[2]) | id_csr_en
|
|
& (_csr_io_decode_0_read_illegal | ~id_csr_ren & _csr_io_decode_0_write_illegal)
|
|
| ~_ibuf_io_inst_0_bits_rvc & id_system_insn & _csr_io_decode_0_system_illegal;
|
|
id_virtual_insn =
|
|
id_ctrl_legal & id_csr_en & ~(~id_csr_ren & _csr_io_decode_0_write_illegal)
|
|
& _csr_io_decode_0_virtual_access_illegal;
|
|
id_xcpt =
|
|
_csr_io_interrupt | _bpu_io_debug_if | _bpu_io_xcpt_if
|
|
| _ibuf_io_inst_0_bits_xcpt0_pf_inst | _ibuf_io_inst_0_bits_xcpt0_gf_inst
|
|
| _ibuf_io_inst_0_bits_xcpt0_ae_inst | _ibuf_io_inst_0_bits_xcpt1_pf_inst
|
|
| _ibuf_io_inst_0_bits_xcpt1_gf_inst | _ibuf_io_inst_0_bits_xcpt1_ae_inst
|
|
| id_virtual_insn | id_illegal_insn;
|
|
bypass_sources_1_1 = ex_reg_valid & ex_ctrl_wxd;
|
|
bypass_sources_2_1 = bypass_sources_3_1 & ~mem_ctrl_mem;
|
|
id_bypass_src_1_1 = bypass_sources_1_1 & _fp_data_hazard_ex_T_3;
|
|
id_bypass_src_1_2 = bypass_sources_2_1 & _fp_data_hazard_mem_T_3;
|
|
do_bypass_1 =
|
|
id_bypass_src_1_0 | id_bypass_src_1_1 | id_bypass_src_1_2 | bypass_sources_3_1
|
|
& _fp_data_hazard_mem_T_3;
|
|
_GEN_15 = id_ctrl_rxs2 & ~do_bypass_1;
|
|
_mem_npc_misaligned_T_3 = ~(_csr_io_status_isa[2]) & _mem_npc_T_4[0];
|
|
_GEN_18 = ex_ctrl_jalr & _csr_io_status_debug;
|
|
_GEN_19 = mem_reg_xcpt_interrupt | mem_reg_xcpt;
|
|
_GEN_20 = mem_reg_valid & _mem_npc_misaligned_T_3;
|
|
mem_xcpt = _GEN_19 | _GEN_20 | mem_reg_valid & mem_ldst_xcpt;
|
|
ctrl_killm = killm_common | mem_xcpt | fpu_kill_mem;
|
|
id_reg_pause <=
|
|
~(_csr_io_time[4:0] == 5'h0 | _csr_io_inhibit_cycle | ibuf_io_kill)
|
|
& (~ctrl_killd & id_ctrl_fence & _ibuf_io_inst_0_bits_inst_bits[23:20] == 4'h0
|
|
| id_reg_pause);
|
|
imem_might_request_reg <= ex_pc_valid | mem_pc_valid | _csr_io_customCSRs_0_value[1];
|
|
if (~ctrl_killd) begin
|
|
automatic logic id_ctrl_decoder_decoded_andMatrixOutputs_61_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
id_ctrl_decoder_decoded_invInputs[2],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[11]};
|
|
automatic logic id_ctrl_decoder_decoded_andMatrixOutputs_40_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[12],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]};
|
|
automatic logic id_ctrl_decoder_decoded_andMatrixOutputs_21_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[12],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[23],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]};
|
|
automatic logic id_ctrl_decoder_decoded_andMatrixOutputs_19_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[12],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
_ibuf_io_inst_0_bits_inst_bits[14],
|
|
id_ctrl_decoder_decoded_invInputs[23],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[29]};
|
|
automatic logic id_ctrl_decoder_decoded_andMatrixOutputs_42_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
_ibuf_io_inst_0_bits_inst_bits[12],
|
|
_ibuf_io_inst_0_bits_inst_bits[14]};
|
|
automatic logic id_ctrl_decoder_decoded_andMatrixOutputs_55_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
_ibuf_io_inst_0_bits_inst_bits[12],
|
|
_ibuf_io_inst_0_bits_inst_bits[14]};
|
|
automatic logic id_ctrl_decoder_decoded_andMatrixOutputs_95_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
_ibuf_io_inst_0_bits_inst_bits[13],
|
|
_ibuf_io_inst_0_bits_inst_bits[14]};
|
|
automatic logic id_ctrl_decoder_decoded_andMatrixOutputs_4_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
_ibuf_io_inst_0_bits_inst_bits[13],
|
|
_ibuf_io_inst_0_bits_inst_bits[14]};
|
|
automatic logic id_ctrl_decoder_decoded_andMatrixOutputs_41_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[2],
|
|
_ibuf_io_inst_0_bits_inst_bits[3],
|
|
id_ctrl_decoder_decoded_invInputs[2],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[13],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
_ibuf_io_inst_0_bits_inst_bits[27],
|
|
_ibuf_io_inst_0_bits_inst_bits[28],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]};
|
|
automatic logic id_ctrl_decoder_decoded_andMatrixOutputs_22_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
id_ctrl_decoder_decoded_invInputs[10],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
id_ctrl_decoder_decoded_invInputs[23],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
_ibuf_io_inst_0_bits_inst_bits[30],
|
|
id_ctrl_decoder_decoded_invInputs[29]};
|
|
automatic logic id_ctrl_decoder_decoded_andMatrixOutputs_113_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[12],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
_ibuf_io_inst_0_bits_inst_bits[14],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
_ibuf_io_inst_0_bits_inst_bits[30],
|
|
id_ctrl_decoder_decoded_invInputs[29]};
|
|
automatic logic id_ctrl_decoder_decoded_andMatrixOutputs_16_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[12],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
_ibuf_io_inst_0_bits_inst_bits[14],
|
|
id_ctrl_decoder_decoded_invInputs[23],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
_ibuf_io_inst_0_bits_inst_bits[30],
|
|
id_ctrl_decoder_decoded_invInputs[29]};
|
|
automatic logic id_ctrl_decoder_decoded_andMatrixOutputs_90_2 =
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[12],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
_ibuf_io_inst_0_bits_inst_bits[14],
|
|
id_ctrl_decoder_decoded_invInputs[23],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
_ibuf_io_inst_0_bits_inst_bits[30],
|
|
id_ctrl_decoder_decoded_invInputs[29]};
|
|
automatic logic _id_ctrl_decoder_decoded_invMatrixOutputs_T_14 =
|
|
|{id_ctrl_decoder_decoded_andMatrixOutputs_82_2,
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
id_ctrl_decoder_decoded_invInputs[2],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[13],
|
|
id_ctrl_decoder_decoded_invInputs[12]},
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_41_2,
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[2],
|
|
_ibuf_io_inst_0_bits_inst_bits[3],
|
|
id_ctrl_decoder_decoded_invInputs[2],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[13],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
_ibuf_io_inst_0_bits_inst_bits[29]}};
|
|
automatic logic _id_ctrl_decoder_decoded_invMatrixOutputs_T_15 =
|
|
|{id_ctrl_decoder_decoded_andMatrixOutputs_88_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_41_2,
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[2],
|
|
_ibuf_io_inst_0_bits_inst_bits[3],
|
|
id_ctrl_decoder_decoded_invInputs[2],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[13],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
_ibuf_io_inst_0_bits_inst_bits[30]}};
|
|
automatic logic _id_ctrl_decoder_decoded_invMatrixOutputs_T_16 =
|
|
|{id_ctrl_decoder_decoded_andMatrixOutputs_74_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_88_2,
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[2],
|
|
_ibuf_io_inst_0_bits_inst_bits[3],
|
|
id_ctrl_decoder_decoded_invInputs[2],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[13],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
_ibuf_io_inst_0_bits_inst_bits[31]}};
|
|
automatic logic id_bypass_src_0_1;
|
|
automatic logic id_bypass_src_0_2;
|
|
automatic logic _GEN_21 =
|
|
|{_ibuf_io_inst_0_bits_xcpt1_pf_inst,
|
|
_ibuf_io_inst_0_bits_xcpt1_gf_inst,
|
|
_ibuf_io_inst_0_bits_xcpt1_ae_inst};
|
|
automatic logic do_bypass;
|
|
automatic logic _GEN_22;
|
|
automatic logic _GEN_23;
|
|
automatic logic [31:0] inst;
|
|
id_bypass_src_0_1 = bypass_sources_1_1 & _fp_data_hazard_ex_T_1;
|
|
id_bypass_src_0_2 = bypass_sources_2_1 & _fp_data_hazard_mem_T_1;
|
|
do_bypass =
|
|
~_GEN_14 | id_bypass_src_0_1 | id_bypass_src_0_2 | bypass_sources_3_1
|
|
& _fp_data_hazard_mem_T_1;
|
|
_GEN_22 = id_ctrl_rxs1 & ~do_bypass;
|
|
_GEN_23 = id_illegal_insn | id_virtual_insn;
|
|
inst =
|
|
_ibuf_io_inst_0_bits_rvc
|
|
? {16'h0, _ibuf_io_inst_0_bits_raw[15:0]}
|
|
: _ibuf_io_inst_0_bits_raw;
|
|
ex_ctrl_fp <= id_ctrl_fp;
|
|
ex_ctrl_branch <=
|
|
|{id_ctrl_decoder_decoded_andMatrixOutputs_61_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_102_2};
|
|
ex_ctrl_jal <= id_ctrl_jal;
|
|
ex_ctrl_jalr <= id_ctrl_jalr;
|
|
ex_ctrl_rxs2 <= id_ctrl_rxs2;
|
|
ex_ctrl_rxs1 <= id_ctrl_rxs1;
|
|
ex_ctrl_sel_alu2 <=
|
|
id_xcpt
|
|
? ((|{_bpu_io_xcpt_if,
|
|
_ibuf_io_inst_0_bits_xcpt0_pf_inst,
|
|
_ibuf_io_inst_0_bits_xcpt0_gf_inst,
|
|
_ibuf_io_inst_0_bits_xcpt0_ae_inst})
|
|
? 3'h0
|
|
: {2'h0, _GEN_21})
|
|
: {1'h0,
|
|
|{id_ctrl_decoder_decoded_andMatrixOutputs_63_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_9_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_0_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_60_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_27_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_120_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_7_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_62_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_61_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_84_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_80_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_64_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_92_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_15_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_48_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_114_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_54_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_42_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_95_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_8_2},
|
|
|{id_ctrl_decoder_decoded_andMatrixOutputs_63_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_9_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_0_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_60_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_27_2,
|
|
id_ctrl_jalr,
|
|
id_ctrl_jal,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_40_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_21_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_92_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_15_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_48_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_19_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_55_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_4_2}};
|
|
ex_ctrl_sel_alu1 <=
|
|
id_xcpt
|
|
? ((|{_bpu_io_xcpt_if,
|
|
_ibuf_io_inst_0_bits_xcpt0_pf_inst,
|
|
_ibuf_io_inst_0_bits_xcpt0_gf_inst,
|
|
_ibuf_io_inst_0_bits_xcpt0_ae_inst,
|
|
_ibuf_io_inst_0_bits_xcpt1_pf_inst,
|
|
_ibuf_io_inst_0_bits_xcpt1_gf_inst,
|
|
_ibuf_io_inst_0_bits_xcpt1_ae_inst})
|
|
? 2'h2
|
|
: 2'h1)
|
|
: {|{&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[2],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
id_ctrl_decoder_decoded_invInputs[4]},
|
|
id_ctrl_jal},
|
|
|{id_ctrl_decoder_decoded_andMatrixOutputs_63_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_9_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_0_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_60_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_120_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_7_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_62_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_84_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_80_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_64_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_14_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_92_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_15_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_12_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_117_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_102_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_48_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_114_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_54_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_8_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_74_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_88_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_101_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_46_2}};
|
|
ex_ctrl_sel_imm <=
|
|
{|{id_ctrl_decoder_decoded_andMatrixOutputs_63_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_9_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_60_2,
|
|
id_ctrl_jalr,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_40_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_21_2,
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
id_ctrl_decoder_decoded_invInputs[2],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[13],
|
|
id_ctrl_decoder_decoded_invInputs[12]},
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_15_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_48_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_19_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_55_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_4_2},
|
|
|{id_ctrl_decoder_decoded_andMatrixOutputs_27_2, id_ctrl_jal},
|
|
|{id_ctrl_decoder_decoded_andMatrixOutputs_61_2,
|
|
id_ctrl_jal,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_42_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_95_2}};
|
|
ex_ctrl_alu_dw <=
|
|
id_xcpt
|
|
| (|{id_ctrl_decoder_decoded_andMatrixOutputs_63_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_9_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_0_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_27_2,
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
id_ctrl_decoder_decoded_invInputs[10],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
id_ctrl_decoder_decoded_invInputs[23],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[29]},
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_7_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_84_2,
|
|
id_ctrl_jal,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_80_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_59_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_92_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_15_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_12_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_99_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_102_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_48_2,
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[12],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
_ibuf_io_inst_0_bits_inst_bits[14],
|
|
id_ctrl_decoder_decoded_invInputs[23],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[29]},
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_74_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_88_2});
|
|
ex_ctrl_alu_fn <=
|
|
id_xcpt
|
|
? 5'h0
|
|
: {1'h0,
|
|
|{&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[13],
|
|
id_ctrl_decoder_decoded_invInputs[12]},
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[13],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
id_ctrl_decoder_decoded_invInputs[23],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]},
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_102_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_22_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_113_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_16_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_90_2},
|
|
|{id_ctrl_decoder_decoded_andMatrixOutputs_15_2,
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[13],
|
|
id_ctrl_decoder_decoded_invInputs[23],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]},
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
id_ctrl_decoder_decoded_invInputs[10],
|
|
_ibuf_io_inst_0_bits_inst_bits[14]},
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[14],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]},
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_102_2,
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[12],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
_ibuf_io_inst_0_bits_inst_bits[14],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]},
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[12],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
_ibuf_io_inst_0_bits_inst_bits[14],
|
|
id_ctrl_decoder_decoded_invInputs[23],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]},
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_8_2},
|
|
|{&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
id_ctrl_decoder_decoded_invInputs[2],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[11],
|
|
id_ctrl_decoder_decoded_invInputs[12]},
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[12],
|
|
_ibuf_io_inst_0_bits_inst_bits[13]},
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[12],
|
|
_ibuf_io_inst_0_bits_inst_bits[13],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]},
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[13],
|
|
_ibuf_io_inst_0_bits_inst_bits[14]},
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[13],
|
|
_ibuf_io_inst_0_bits_inst_bits[14],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]},
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
id_ctrl_decoder_decoded_invInputs[2],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
_ibuf_io_inst_0_bits_inst_bits[13],
|
|
_ibuf_io_inst_0_bits_inst_bits[14]},
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[13],
|
|
_ibuf_io_inst_0_bits_inst_bits[25],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]},
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[13],
|
|
_ibuf_io_inst_0_bits_inst_bits[14],
|
|
_ibuf_io_inst_0_bits_inst_bits[25],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]},
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_22_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_113_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_16_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_90_2},
|
|
|{id_ctrl_decoder_decoded_andMatrixOutputs_80_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_64_2,
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
id_ctrl_decoder_decoded_invInputs[2],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
_ibuf_io_inst_0_bits_inst_bits[12],
|
|
id_ctrl_decoder_decoded_invInputs[11]},
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_48_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_114_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_54_2,
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[12],
|
|
_ibuf_io_inst_0_bits_inst_bits[14],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]},
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
id_ctrl_decoder_decoded_invInputs[2],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
_ibuf_io_inst_0_bits_inst_bits[12],
|
|
_ibuf_io_inst_0_bits_inst_bits[14]},
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[12],
|
|
_ibuf_io_inst_0_bits_inst_bits[13],
|
|
_ibuf_io_inst_0_bits_inst_bits[14]},
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[12],
|
|
_ibuf_io_inst_0_bits_inst_bits[25],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]},
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[12],
|
|
_ibuf_io_inst_0_bits_inst_bits[14],
|
|
_ibuf_io_inst_0_bits_inst_bits[25],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]}}};
|
|
ex_ctrl_mem <= id_ctrl_mem;
|
|
ex_ctrl_mem_cmd <=
|
|
{1'h0,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_12_2,
|
|
_id_ctrl_decoder_decoded_invMatrixOutputs_T_16,
|
|
_id_ctrl_decoder_decoded_invMatrixOutputs_T_15,
|
|
_id_ctrl_decoder_decoded_invMatrixOutputs_T_14};
|
|
ex_ctrl_rfs1 <=
|
|
|{id_ctrl_rfs3,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_18_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_6_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_86_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_70_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_111_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_73_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_87_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_65_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_26_2};
|
|
ex_ctrl_rfs2 <=
|
|
|{id_ctrl_rfs3,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_18_2,
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[2],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
id_ctrl_decoder_decoded_invInputs[2],
|
|
_ibuf_io_inst_0_bits_inst_bits[5],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[13],
|
|
id_ctrl_decoder_decoded_invInputs[12]},
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_6_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_86_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_70_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_87_2};
|
|
ex_ctrl_wfd <=
|
|
|{id_ctrl_rfs3,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_18_2,
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[2],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
id_ctrl_decoder_decoded_invInputs[2],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
id_ctrl_decoder_decoded_invInputs[4],
|
|
_ibuf_io_inst_0_bits_inst_bits[13],
|
|
id_ctrl_decoder_decoded_invInputs[12]},
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_70_2,
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[10],
|
|
id_ctrl_decoder_decoded_invInputs[12],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
_ibuf_io_inst_0_bits_inst_bits[29],
|
|
id_ctrl_decoder_decoded_invInputs[28],
|
|
id_ctrl_decoder_decoded_invInputs[29]},
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_23_2,
|
|
&{_ibuf_io_inst_0_bits_inst_bits[0],
|
|
_ibuf_io_inst_0_bits_inst_bits[1],
|
|
id_ctrl_decoder_decoded_invInputs[0],
|
|
id_ctrl_decoder_decoded_invInputs[1],
|
|
_ibuf_io_inst_0_bits_inst_bits[4],
|
|
id_ctrl_decoder_decoded_invInputs[3],
|
|
_ibuf_io_inst_0_bits_inst_bits[6],
|
|
id_ctrl_decoder_decoded_invInputs[18],
|
|
id_ctrl_decoder_decoded_invInputs[19],
|
|
id_ctrl_decoder_decoded_invInputs[20],
|
|
id_ctrl_decoder_decoded_invInputs[21],
|
|
id_ctrl_decoder_decoded_invInputs[22],
|
|
_ibuf_io_inst_0_bits_inst_bits[25],
|
|
id_ctrl_decoder_decoded_invInputs[24],
|
|
id_ctrl_decoder_decoded_invInputs[25],
|
|
id_ctrl_decoder_decoded_invInputs[26],
|
|
id_ctrl_decoder_decoded_invInputs[27],
|
|
_ibuf_io_inst_0_bits_inst_bits[30],
|
|
id_ctrl_decoder_decoded_invInputs[29]},
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_87_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_101_2,
|
|
id_ctrl_decoder_decoded_andMatrixOutputs_46_2};
|
|
ex_ctrl_div <= id_ctrl_div;
|
|
ex_ctrl_wxd <= id_ctrl_wxd;
|
|
ex_ctrl_csr <=
|
|
id_system_insn & id_ctrl_mem ? 3'h0 : id_csr_ren ? 3'h2 : id_ctrl_csr;
|
|
ex_ctrl_fence_i <= id_ctrl_fence_i;
|
|
ex_reg_rvc <= id_xcpt & _GEN_21 | _ibuf_io_inst_0_bits_rvc;
|
|
ex_reg_flush_pipe <=
|
|
id_ctrl_fence_i | id_system_insn | id_csr_en & ~id_csr_ren
|
|
& _csr_io_decode_0_write_flush;
|
|
ex_reg_load_use <= mem_reg_valid & data_hazard_mem & mem_ctrl_mem;
|
|
ex_reg_mem_size <=
|
|
{id_ctrl_decoder_decoded_andMatrixOutputs_12_2,
|
|
_id_ctrl_decoder_decoded_invMatrixOutputs_T_16,
|
|
_id_ctrl_decoder_decoded_invMatrixOutputs_T_15,
|
|
_id_ctrl_decoder_decoded_invMatrixOutputs_T_14} == 4'h5
|
|
? {|_ibuf_io_inst_0_bits_inst_rs2, |_ibuf_io_inst_0_bits_inst_rs1}
|
|
: _ibuf_io_inst_0_bits_inst_bits[13:12];
|
|
ex_reg_rs_bypass_0 <= ~_GEN_23 & do_bypass;
|
|
ex_reg_rs_bypass_1 <= do_bypass_1;
|
|
ex_reg_rs_lsb_0 <=
|
|
_GEN_23
|
|
? inst[1:0]
|
|
: _GEN_22
|
|
? id_rs_0[1:0]
|
|
: _GEN_14 ? (id_bypass_src_0_1 ? 2'h1 : {1'h1, ~id_bypass_src_0_2}) : 2'h0;
|
|
ex_reg_rs_lsb_1 <=
|
|
_GEN_15
|
|
? id_rs_1[1:0]
|
|
: id_bypass_src_1_0
|
|
? 2'h0
|
|
: id_bypass_src_1_1 ? 2'h1 : {1'h1, ~id_bypass_src_1_2};
|
|
if (_GEN_23)
|
|
ex_reg_rs_msb_0 <= {32'h0, inst[31:2]};
|
|
else if (_GEN_22)
|
|
ex_reg_rs_msb_0 <= id_rs_0[63:2];
|
|
end
|
|
if (_GEN_17) begin
|
|
end
|
|
else
|
|
mem_ctrl_fp <= ex_ctrl_fp;
|
|
mem_ctrl_rocc <= _GEN_17 & mem_ctrl_rocc;
|
|
if (_GEN_17) begin
|
|
end
|
|
else begin
|
|
mem_ctrl_branch <= ex_ctrl_branch;
|
|
mem_ctrl_jal <= ex_ctrl_jal;
|
|
mem_ctrl_jalr <= ex_ctrl_jalr;
|
|
mem_ctrl_rxs2 <= ex_ctrl_rxs2;
|
|
mem_ctrl_rxs1 <= ex_ctrl_rxs1;
|
|
mem_ctrl_mem <= ex_ctrl_mem;
|
|
mem_ctrl_rfs1 <= ex_ctrl_rfs1;
|
|
mem_ctrl_rfs2 <= ex_ctrl_rfs2;
|
|
mem_ctrl_wfd <= ex_ctrl_wfd;
|
|
end
|
|
mem_ctrl_mul <= _GEN_17 & mem_ctrl_mul;
|
|
if (_GEN_17) begin
|
|
end
|
|
else begin
|
|
mem_ctrl_div <= ex_ctrl_div;
|
|
mem_ctrl_wxd <= ex_ctrl_wxd;
|
|
mem_ctrl_csr <= ex_ctrl_csr;
|
|
mem_ctrl_fence_i <= _GEN_18 | ex_ctrl_fence_i;
|
|
end
|
|
mem_ctrl_vec <= _GEN_17 & mem_ctrl_vec;
|
|
if (mem_pc_valid) begin
|
|
wb_ctrl_rocc <= mem_ctrl_rocc;
|
|
wb_ctrl_rxs2 <= mem_ctrl_rxs2;
|
|
wb_ctrl_rxs1 <= mem_ctrl_rxs1;
|
|
wb_ctrl_mem <= mem_ctrl_mem;
|
|
wb_ctrl_rfs1 <= mem_ctrl_rfs1;
|
|
wb_ctrl_rfs2 <= mem_ctrl_rfs2;
|
|
wb_ctrl_wfd <= mem_ctrl_wfd;
|
|
wb_ctrl_div <= mem_ctrl_div;
|
|
wb_ctrl_wxd <= mem_ctrl_wxd;
|
|
wb_ctrl_csr <= mem_ctrl_csr;
|
|
wb_ctrl_fence_i <= mem_ctrl_fence_i;
|
|
wb_ctrl_vec <= mem_ctrl_vec;
|
|
wb_reg_cause <=
|
|
_GEN_19
|
|
? mem_reg_cause
|
|
: {60'h0, _GEN_20 ? 4'h0 : mem_debug_breakpoint ? 4'hE : 4'h3};
|
|
wb_reg_pc <= mem_reg_pc;
|
|
wb_reg_hls_or_dv <= mem_reg_hls_or_dv;
|
|
wb_reg_inst <= mem_reg_inst;
|
|
wb_reg_raw_inst <= mem_reg_raw_inst;
|
|
wb_reg_wdata <=
|
|
~mem_reg_xcpt & mem_ctrl_fp & mem_ctrl_wxd
|
|
? io_fpu_toint_data
|
|
: ~mem_reg_xcpt & (mem_ctrl_jalr ^ _mem_npc_misaligned_T_3)
|
|
? {{30{_mem_br_target_T_9[33]}}, _mem_br_target_T_9}
|
|
: mem_reg_wdata;
|
|
end
|
|
ex_reg_xcpt_interrupt <= ~ibuf_io_kill & _ibuf_io_inst_0_valid & _csr_io_interrupt;
|
|
ex_reg_valid <= ~ctrl_killd;
|
|
ex_reg_xcpt <= ~ctrl_killd & id_xcpt;
|
|
if (~ctrl_killd | _csr_io_interrupt | _ibuf_io_inst_0_bits_replay) begin
|
|
ex_reg_cause <=
|
|
_csr_io_interrupt
|
|
? _csr_io_interrupt_cause
|
|
: {59'h0,
|
|
_bpu_io_debug_if
|
|
? 5'hE
|
|
: _bpu_io_xcpt_if
|
|
? 5'h3
|
|
: _ibuf_io_inst_0_bits_xcpt0_pf_inst
|
|
? 5'hC
|
|
: _ibuf_io_inst_0_bits_xcpt0_gf_inst
|
|
? 5'h14
|
|
: _ibuf_io_inst_0_bits_xcpt0_ae_inst
|
|
? 5'h1
|
|
: _ibuf_io_inst_0_bits_xcpt1_pf_inst
|
|
? 5'hC
|
|
: _ibuf_io_inst_0_bits_xcpt1_gf_inst
|
|
? 5'h14
|
|
: _ibuf_io_inst_0_bits_xcpt1_ae_inst
|
|
? 5'h1
|
|
: id_virtual_insn ? 5'h16 : 5'h2};
|
|
ex_reg_pc <= _ibuf_io_pc;
|
|
ex_reg_inst <= _ibuf_io_inst_0_bits_inst_bits;
|
|
ex_reg_raw_inst <= _ibuf_io_inst_0_bits_raw;
|
|
end
|
|
ex_reg_replay <= ~ibuf_io_kill & _ibuf_io_inst_0_valid & _ibuf_io_inst_0_bits_replay;
|
|
mem_reg_xcpt_interrupt <= ~ibuf_io_kill & ex_reg_xcpt_interrupt;
|
|
mem_reg_valid <= ~ctrl_killx;
|
|
if (_GEN_17) begin
|
|
end
|
|
else
|
|
mem_reg_rvc <= ex_reg_rvc;
|
|
mem_reg_xcpt <= ~ctrl_killx & (ex_reg_xcpt_interrupt | ex_reg_xcpt);
|
|
mem_reg_replay <= ~ibuf_io_kill & replay_ex;
|
|
if (_GEN_17) begin
|
|
end
|
|
else begin
|
|
automatic logic _io_dmem_req_bits_no_resp_T_3 = ex_ctrl_mem_cmd == 5'h7;
|
|
automatic logic _mem_reg_store_T_5 = ex_ctrl_mem_cmd == 5'h4;
|
|
automatic logic _mem_reg_store_T_6 = ex_ctrl_mem_cmd == 5'h9;
|
|
automatic logic _mem_reg_store_T_7 = ex_ctrl_mem_cmd == 5'hA;
|
|
automatic logic _mem_reg_store_T_8 = ex_ctrl_mem_cmd == 5'hB;
|
|
automatic logic _mem_reg_store_T_12 = ex_ctrl_mem_cmd == 5'h8;
|
|
automatic logic _mem_reg_store_T_13 = ex_ctrl_mem_cmd == 5'hC;
|
|
automatic logic _mem_reg_store_T_14 = ex_ctrl_mem_cmd == 5'hD;
|
|
automatic logic _mem_reg_store_T_15 = ex_ctrl_mem_cmd == 5'hE;
|
|
automatic logic _mem_reg_store_T_16 = ex_ctrl_mem_cmd == 5'hF;
|
|
mem_reg_flush_pipe <= _GEN_18 | ex_reg_flush_pipe;
|
|
mem_reg_cause <= ex_reg_cause;
|
|
mem_reg_slow_bypass <= _io_dmem_req_bits_no_resp_T_3 | ~(ex_reg_mem_size[1]);
|
|
mem_reg_load <=
|
|
ex_ctrl_mem
|
|
& (ex_ctrl_mem_cmd == 5'h0 | ex_ctrl_mem_cmd == 5'h10 | ex_ctrl_mem_cmd == 5'h6
|
|
| _io_dmem_req_bits_no_resp_T_3 | _mem_reg_store_T_5 | _mem_reg_store_T_6
|
|
| _mem_reg_store_T_7 | _mem_reg_store_T_8 | _mem_reg_store_T_12
|
|
| _mem_reg_store_T_13 | _mem_reg_store_T_14 | _mem_reg_store_T_15
|
|
| _mem_reg_store_T_16);
|
|
mem_reg_store <=
|
|
ex_ctrl_mem
|
|
& (ex_ctrl_mem_cmd == 5'h1 | ex_ctrl_mem_cmd == 5'h11
|
|
| _io_dmem_req_bits_no_resp_T_3 | _mem_reg_store_T_5 | _mem_reg_store_T_6
|
|
| _mem_reg_store_T_7 | _mem_reg_store_T_8 | _mem_reg_store_T_12
|
|
| _mem_reg_store_T_13 | _mem_reg_store_T_14 | _mem_reg_store_T_15
|
|
| _mem_reg_store_T_16);
|
|
mem_reg_pc <= ex_reg_pc;
|
|
mem_reg_inst <= ex_reg_inst;
|
|
mem_reg_hls_or_dv <= _csr_io_status_dv;
|
|
mem_reg_raw_inst <= ex_reg_raw_inst;
|
|
mem_reg_wdata <= _alu_io_out;
|
|
end
|
|
if (_GEN_16 | ~(ex_pc_valid & ex_ctrl_rxs2 & ex_ctrl_mem)) begin
|
|
end
|
|
else begin
|
|
automatic logic [3:0][63:0] _GEN_24 =
|
|
{{ex_rs_1}, {{2{ex_rs_1[31:0]}}}, {{4{ex_rs_1[15:0]}}}, {{8{ex_rs_1[7:0]}}}};
|
|
mem_reg_rs2 <= _GEN_24[ex_reg_mem_size];
|
|
end
|
|
if (_GEN_17) begin
|
|
end
|
|
else
|
|
mem_br_taken <= _alu_io_cmp_out;
|
|
wb_reg_valid <= ~ctrl_killm;
|
|
wb_reg_xcpt <= mem_xcpt & ~take_pc_wb;
|
|
wb_reg_replay <= (dcache_kill_mem | mem_reg_replay | fpu_kill_mem) & ~take_pc_wb;
|
|
wb_reg_flush_pipe <= ~ctrl_killm & mem_reg_flush_pipe;
|
|
if (~ctrl_killd & _GEN_15)
|
|
ex_reg_rs_msb_1 <= id_rs_1[63:2];
|
|
div_io_kill_REG <= _div_io_req_ready & div_io_req_valid;
|
|
dcache_blocked_blocked <=
|
|
~io_dmem_req_ready & ~io_dmem_perf_grant
|
|
& (dcache_blocked_blocked | io_dmem_req_valid_0 | io_dmem_s2_nack);
|
|
coreMonitorBundle_rd0val_REG <= ex_rs_0;
|
|
coreMonitorBundle_rd0val_REG_1 <= coreMonitorBundle_rd0val_REG;
|
|
coreMonitorBundle_rd1val_REG <= ex_rs_1;
|
|
coreMonitorBundle_rd1val_REG_1 <= coreMonitorBundle_rd1val_REG;
|
|
if (reset) begin
|
|
id_reg_fence <= 1'h0;
|
|
_r <= 32'h0;
|
|
_id_stall_fpu_r <= 32'h0;
|
|
end
|
|
else begin
|
|
automatic logic [31:0] _GEN_25;
|
|
automatic logic _GEN_26;
|
|
automatic logic [31:0] _id_stall_fpu_T_4;
|
|
automatic logic _id_stall_fpu_T_7 =
|
|
((wb_dcache_miss | wb_ctrl_vec) & wb_ctrl_wfd | io_fpu_sboard_set) & wb_valid;
|
|
automatic logic [31:0] _id_stall_fpu_T_5;
|
|
automatic logic _id_stall_fpu_T_9 =
|
|
dmem_resp_replay & io_dmem_resp_bits_tag[0];
|
|
automatic logic [31:0] _id_stall_fpu_T_13;
|
|
automatic logic _id_stall_fpu_T_14 = _id_stall_fpu_T_7 | _id_stall_fpu_T_9;
|
|
_GEN_25 = r & ~(ll_wen ? 32'h1 << ll_waddr : 32'h0);
|
|
_GEN_26 = wb_set_sboard & wb_wen;
|
|
_id_stall_fpu_T_4 = 32'h1 << wb_reg_inst[11:7];
|
|
_id_stall_fpu_T_5 = _id_stall_fpu_T_7 ? _id_stall_fpu_T_4 : 32'h0;
|
|
_id_stall_fpu_T_13 =
|
|
(_id_stall_fpu_r | _id_stall_fpu_T_5)
|
|
& ~(_id_stall_fpu_T_9 ? 32'h1 << io_dmem_resp_bits_tag[5:1] : 32'h0);
|
|
id_reg_fence <=
|
|
~ctrl_killd & (id_ctrl_fence | id_ctrl_amo & _ibuf_io_inst_0_bits_inst_bits[26])
|
|
| id_mem_busy & id_reg_fence;
|
|
if (ll_wen | _GEN_26)
|
|
_r <= _GEN_25 | (_GEN_26 ? _id_stall_fpu_T_4 : 32'h0);
|
|
else if (ll_wen)
|
|
_r <= _GEN_25;
|
|
_id_stall_fpu_r <=
|
|
_id_stall_fpu_T_14 | io_fpu_sboard_clr
|
|
? _id_stall_fpu_T_13
|
|
& ~(io_fpu_sboard_clr ? 32'h1 << io_fpu_sboard_clra : 32'h0)
|
|
: _id_stall_fpu_T_14
|
|
? _id_stall_fpu_T_13
|
|
: {32{_id_stall_fpu_T_7}} & _id_stall_fpu_T_5 | _id_stall_fpu_r;
|
|
end
|
|
end // always @(posedge)
|
|
IBuf ibuf (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_imem_ready (io_imem_resp_ready),
|
|
.io_imem_valid (io_imem_resp_valid),
|
|
.io_imem_bits_pc (io_imem_resp_bits_pc),
|
|
.io_imem_bits_data (io_imem_resp_bits_data),
|
|
.io_imem_bits_xcpt_pf_inst (io_imem_resp_bits_xcpt_pf_inst),
|
|
.io_imem_bits_xcpt_gf_inst (io_imem_resp_bits_xcpt_gf_inst),
|
|
.io_imem_bits_xcpt_ae_inst (io_imem_resp_bits_xcpt_ae_inst),
|
|
.io_imem_bits_replay (io_imem_resp_bits_replay),
|
|
.io_kill (ibuf_io_kill),
|
|
.io_pc (_ibuf_io_pc),
|
|
.io_inst_0_ready (~_ctrl_stalld_T_32),
|
|
.io_inst_0_valid (_ibuf_io_inst_0_valid),
|
|
.io_inst_0_bits_xcpt0_pf_inst (_ibuf_io_inst_0_bits_xcpt0_pf_inst),
|
|
.io_inst_0_bits_xcpt0_gf_inst (_ibuf_io_inst_0_bits_xcpt0_gf_inst),
|
|
.io_inst_0_bits_xcpt0_ae_inst (_ibuf_io_inst_0_bits_xcpt0_ae_inst),
|
|
.io_inst_0_bits_xcpt1_pf_inst (_ibuf_io_inst_0_bits_xcpt1_pf_inst),
|
|
.io_inst_0_bits_xcpt1_gf_inst (_ibuf_io_inst_0_bits_xcpt1_gf_inst),
|
|
.io_inst_0_bits_xcpt1_ae_inst (_ibuf_io_inst_0_bits_xcpt1_ae_inst),
|
|
.io_inst_0_bits_replay (_ibuf_io_inst_0_bits_replay),
|
|
.io_inst_0_bits_rvc (_ibuf_io_inst_0_bits_rvc),
|
|
.io_inst_0_bits_inst_bits (_ibuf_io_inst_0_bits_inst_bits),
|
|
.io_inst_0_bits_inst_rd (_ibuf_io_inst_0_bits_inst_rd),
|
|
.io_inst_0_bits_inst_rs1 (_ibuf_io_inst_0_bits_inst_rs1),
|
|
.io_inst_0_bits_inst_rs2 (_ibuf_io_inst_0_bits_inst_rs2),
|
|
.io_inst_0_bits_inst_rs3 (_ibuf_io_inst_0_bits_inst_rs3),
|
|
.io_inst_0_bits_raw (_ibuf_io_inst_0_bits_raw)
|
|
);
|
|
rf_31x64 rf_ext (
|
|
.R0_addr (~_ibuf_io_inst_0_bits_inst_rs2),
|
|
.R0_en (1'h1),
|
|
.R0_clk (clock),
|
|
.R0_data (_rf_ext_R0_data),
|
|
.R1_addr (~_ibuf_io_inst_0_bits_inst_rs1),
|
|
.R1_en (1'h1),
|
|
.R1_clk (clock),
|
|
.R1_data (_rf_ext_R1_data),
|
|
.W0_addr (~rf_waddr),
|
|
.W0_en (rf_wen & _GEN_8),
|
|
.W0_clk (clock),
|
|
.W0_data (rf_wdata)
|
|
);
|
|
CSRFile csr (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_ungated_clock (clock),
|
|
.io_interrupts_debug (io_interrupts_debug),
|
|
.io_interrupts_mtip (io_interrupts_mtip),
|
|
.io_interrupts_msip (io_interrupts_msip),
|
|
.io_interrupts_meip (io_interrupts_meip),
|
|
.io_rw_addr (wb_reg_inst[31:20]),
|
|
.io_rw_cmd (wb_ctrl_csr & {wb_reg_valid, 2'h3}),
|
|
.io_rw_rdata (_csr_io_rw_rdata),
|
|
.io_rw_wdata (wb_reg_wdata),
|
|
.io_decode_0_inst (_ibuf_io_inst_0_bits_inst_bits),
|
|
.io_decode_0_fp_illegal (_csr_io_decode_0_fp_illegal),
|
|
.io_decode_0_fp_csr (_csr_io_decode_0_fp_csr),
|
|
.io_decode_0_read_illegal (_csr_io_decode_0_read_illegal),
|
|
.io_decode_0_write_illegal (_csr_io_decode_0_write_illegal),
|
|
.io_decode_0_write_flush (_csr_io_decode_0_write_flush),
|
|
.io_decode_0_system_illegal (_csr_io_decode_0_system_illegal),
|
|
.io_decode_0_virtual_access_illegal (_csr_io_decode_0_virtual_access_illegal),
|
|
.io_csr_stall (_csr_io_csr_stall),
|
|
.io_eret (_csr_io_eret),
|
|
.io_singleStep (_csr_io_singleStep),
|
|
.io_status_debug (_csr_io_status_debug),
|
|
.io_status_wfi (io_wfi),
|
|
.io_status_isa (_csr_io_status_isa),
|
|
.io_status_dv (_csr_io_status_dv),
|
|
.io_status_v (_csr_io_status_v),
|
|
.io_evec (_csr_io_evec),
|
|
.io_exception (wb_xcpt),
|
|
.io_retire (wb_valid),
|
|
.io_cause
|
|
(wb_reg_xcpt
|
|
? wb_reg_cause
|
|
: {59'h0,
|
|
_GEN_2
|
|
? 5'hF
|
|
: _GEN_3
|
|
? 5'hD
|
|
: {2'h0, _GEN_4 ? 3'h7 : _GEN_5 ? 3'h5 : {1'h1, _GEN_6, 1'h0}}}),
|
|
.io_pc (wb_reg_pc),
|
|
.io_tval
|
|
(wb_xcpt & (tval_any_addr | wb_reg_cause == 64'h2)
|
|
? {wb_reg_wdata[63:33] == 31'h0 | (&(wb_reg_wdata[63:33]))
|
|
? wb_reg_wdata[33]
|
|
: ~(wb_reg_wdata[32]),
|
|
wb_reg_wdata[32:0]}
|
|
: 34'h0),
|
|
.io_gva
|
|
(wb_xcpt & (tval_any_addr & _csr_io_status_v | ~wb_reg_xcpt & wb_reg_hls_or_dv)),
|
|
.io_time (_csr_io_time),
|
|
.io_fcsr_rm (io_fpu_fcsr_rm),
|
|
.io_fcsr_flags_valid (io_fpu_fcsr_flags_valid),
|
|
.io_fcsr_flags_bits
|
|
(io_fpu_fcsr_flags_valid ? io_fpu_fcsr_flags_bits : 5'h0),
|
|
.io_interrupt (_csr_io_interrupt),
|
|
.io_interrupt_cause (_csr_io_interrupt_cause),
|
|
.io_bp_0_control_action (_csr_io_bp_0_control_action),
|
|
.io_bp_0_control_tmatch (_csr_io_bp_0_control_tmatch),
|
|
.io_bp_0_control_x (_csr_io_bp_0_control_x),
|
|
.io_bp_0_control_w (_csr_io_bp_0_control_w),
|
|
.io_bp_0_control_r (_csr_io_bp_0_control_r),
|
|
.io_bp_0_address (_csr_io_bp_0_address),
|
|
.io_pmp_0_cfg_l (io_ptw_pmp_0_cfg_l),
|
|
.io_pmp_0_cfg_a (io_ptw_pmp_0_cfg_a),
|
|
.io_pmp_0_cfg_x (io_ptw_pmp_0_cfg_x),
|
|
.io_pmp_0_cfg_w (io_ptw_pmp_0_cfg_w),
|
|
.io_pmp_0_cfg_r (io_ptw_pmp_0_cfg_r),
|
|
.io_pmp_0_addr (io_ptw_pmp_0_addr),
|
|
.io_pmp_0_mask (io_ptw_pmp_0_mask),
|
|
.io_pmp_1_cfg_l (io_ptw_pmp_1_cfg_l),
|
|
.io_pmp_1_cfg_a (io_ptw_pmp_1_cfg_a),
|
|
.io_pmp_1_cfg_x (io_ptw_pmp_1_cfg_x),
|
|
.io_pmp_1_cfg_w (io_ptw_pmp_1_cfg_w),
|
|
.io_pmp_1_cfg_r (io_ptw_pmp_1_cfg_r),
|
|
.io_pmp_1_addr (io_ptw_pmp_1_addr),
|
|
.io_pmp_1_mask (io_ptw_pmp_1_mask),
|
|
.io_pmp_2_cfg_l (io_ptw_pmp_2_cfg_l),
|
|
.io_pmp_2_cfg_a (io_ptw_pmp_2_cfg_a),
|
|
.io_pmp_2_cfg_x (io_ptw_pmp_2_cfg_x),
|
|
.io_pmp_2_cfg_w (io_ptw_pmp_2_cfg_w),
|
|
.io_pmp_2_cfg_r (io_ptw_pmp_2_cfg_r),
|
|
.io_pmp_2_addr (io_ptw_pmp_2_addr),
|
|
.io_pmp_2_mask (io_ptw_pmp_2_mask),
|
|
.io_pmp_3_cfg_l (io_ptw_pmp_3_cfg_l),
|
|
.io_pmp_3_cfg_a (io_ptw_pmp_3_cfg_a),
|
|
.io_pmp_3_cfg_x (io_ptw_pmp_3_cfg_x),
|
|
.io_pmp_3_cfg_w (io_ptw_pmp_3_cfg_w),
|
|
.io_pmp_3_cfg_r (io_ptw_pmp_3_cfg_r),
|
|
.io_pmp_3_addr (io_ptw_pmp_3_addr),
|
|
.io_pmp_3_mask (io_ptw_pmp_3_mask),
|
|
.io_pmp_4_cfg_l (io_ptw_pmp_4_cfg_l),
|
|
.io_pmp_4_cfg_a (io_ptw_pmp_4_cfg_a),
|
|
.io_pmp_4_cfg_x (io_ptw_pmp_4_cfg_x),
|
|
.io_pmp_4_cfg_w (io_ptw_pmp_4_cfg_w),
|
|
.io_pmp_4_cfg_r (io_ptw_pmp_4_cfg_r),
|
|
.io_pmp_4_addr (io_ptw_pmp_4_addr),
|
|
.io_pmp_4_mask (io_ptw_pmp_4_mask),
|
|
.io_pmp_5_cfg_l (io_ptw_pmp_5_cfg_l),
|
|
.io_pmp_5_cfg_a (io_ptw_pmp_5_cfg_a),
|
|
.io_pmp_5_cfg_x (io_ptw_pmp_5_cfg_x),
|
|
.io_pmp_5_cfg_w (io_ptw_pmp_5_cfg_w),
|
|
.io_pmp_5_cfg_r (io_ptw_pmp_5_cfg_r),
|
|
.io_pmp_5_addr (io_ptw_pmp_5_addr),
|
|
.io_pmp_5_mask (io_ptw_pmp_5_mask),
|
|
.io_pmp_6_cfg_l (io_ptw_pmp_6_cfg_l),
|
|
.io_pmp_6_cfg_a (io_ptw_pmp_6_cfg_a),
|
|
.io_pmp_6_cfg_x (io_ptw_pmp_6_cfg_x),
|
|
.io_pmp_6_cfg_w (io_ptw_pmp_6_cfg_w),
|
|
.io_pmp_6_cfg_r (io_ptw_pmp_6_cfg_r),
|
|
.io_pmp_6_addr (io_ptw_pmp_6_addr),
|
|
.io_pmp_6_mask (io_ptw_pmp_6_mask),
|
|
.io_pmp_7_cfg_l (io_ptw_pmp_7_cfg_l),
|
|
.io_pmp_7_cfg_a (io_ptw_pmp_7_cfg_a),
|
|
.io_pmp_7_cfg_x (io_ptw_pmp_7_cfg_x),
|
|
.io_pmp_7_cfg_w (io_ptw_pmp_7_cfg_w),
|
|
.io_pmp_7_cfg_r (io_ptw_pmp_7_cfg_r),
|
|
.io_pmp_7_addr (io_ptw_pmp_7_addr),
|
|
.io_pmp_7_mask (io_ptw_pmp_7_mask),
|
|
.io_inhibit_cycle (_csr_io_inhibit_cycle),
|
|
.io_inst_0
|
|
({(&(wb_reg_raw_inst[1:0])) ? wb_reg_inst[31:16] : 16'h0, wb_reg_raw_inst[15:0]}),
|
|
.io_trace_0_valid (_csr_io_trace_0_valid),
|
|
.io_trace_0_iaddr (_csr_io_trace_0_iaddr),
|
|
.io_trace_0_insn (_csr_io_trace_0_insn),
|
|
.io_trace_0_exception (_csr_io_trace_0_exception),
|
|
.io_customCSRs_0_value (_csr_io_customCSRs_0_value)
|
|
);
|
|
BreakpointUnit bpu (
|
|
.io_status_debug (_csr_io_status_debug),
|
|
.io_bp_0_control_action (_csr_io_bp_0_control_action),
|
|
.io_bp_0_control_tmatch (_csr_io_bp_0_control_tmatch),
|
|
.io_bp_0_control_x (_csr_io_bp_0_control_x),
|
|
.io_bp_0_control_w (_csr_io_bp_0_control_w),
|
|
.io_bp_0_control_r (_csr_io_bp_0_control_r),
|
|
.io_bp_0_address (_csr_io_bp_0_address),
|
|
.io_pc (_ibuf_io_pc[32:0]),
|
|
.io_ea (mem_reg_wdata[32:0]),
|
|
.io_xcpt_if (_bpu_io_xcpt_if),
|
|
.io_xcpt_ld (_bpu_io_xcpt_ld),
|
|
.io_xcpt_st (_bpu_io_xcpt_st),
|
|
.io_debug_if (_bpu_io_debug_if),
|
|
.io_debug_ld (_bpu_io_debug_ld),
|
|
.io_debug_st (_bpu_io_debug_st)
|
|
);
|
|
RocketALU alu (
|
|
.io_dw (ex_ctrl_alu_dw),
|
|
.io_fn (ex_ctrl_alu_fn),
|
|
.io_in2
|
|
(ex_ctrl_sel_alu2 == 3'h1
|
|
? {{60{_ex_op2_T_1[3]}}, _ex_op2_T_1}
|
|
: ex_ctrl_sel_alu2 == 3'h3
|
|
? {{33{ex_imm_sign}},
|
|
_ex_imm_b4_1_T ? ex_reg_inst[30:20] : {11{ex_imm_sign}},
|
|
ex_ctrl_sel_imm != 3'h2 & ex_ctrl_sel_imm != 3'h3
|
|
? {8{ex_imm_sign}}
|
|
: ex_reg_inst[19:12],
|
|
~(_ex_imm_b4_1_T | _ex_imm_b0_T_4)
|
|
& (ex_ctrl_sel_imm == 3'h3
|
|
? ex_reg_inst[20]
|
|
: _ex_imm_b4_1_T_2 ? ex_reg_inst[7] : ex_imm_sign),
|
|
_ex_imm_b4_1_T | _ex_imm_b0_T_4 ? 6'h0 : ex_reg_inst[30:25],
|
|
_ex_imm_b4_1_T
|
|
? 4'h0
|
|
: _ex_imm_b0_T | _ex_imm_b4_1_T_2
|
|
? ex_reg_inst[11:8]
|
|
: _ex_imm_b0_T_4 ? ex_reg_inst[19:16] : ex_reg_inst[24:21],
|
|
_ex_imm_b0_T
|
|
? ex_reg_inst[7]
|
|
: ex_ctrl_sel_imm == 3'h4
|
|
? ex_reg_inst[20]
|
|
: _ex_imm_b0_T_4 & ex_reg_inst[15]}
|
|
: ex_ctrl_sel_alu2 == 3'h2 ? ex_rs_1 : 64'h0),
|
|
.io_in1 (_GEN_0[ex_ctrl_sel_alu1]),
|
|
.io_out (_alu_io_out),
|
|
.io_adder_out (_alu_io_adder_out),
|
|
.io_cmp_out (_alu_io_cmp_out)
|
|
);
|
|
MulDiv div (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_req_ready (_div_io_req_ready),
|
|
.io_req_valid (div_io_req_valid),
|
|
.io_req_bits_fn (ex_ctrl_alu_fn),
|
|
.io_req_bits_dw (ex_ctrl_alu_dw),
|
|
.io_req_bits_in1 (ex_rs_0),
|
|
.io_req_bits_in2 (ex_rs_1),
|
|
.io_req_bits_tag (ex_reg_inst[11:7]),
|
|
.io_kill (killm_common & div_io_kill_REG),
|
|
.io_resp_ready (_ll_arb_io_in_0_ready),
|
|
.io_resp_valid (_div_io_resp_valid),
|
|
.io_resp_bits_data (_div_io_resp_bits_data),
|
|
.io_resp_bits_tag (_div_io_resp_bits_tag)
|
|
);
|
|
Arbiter3_LLWB ll_arb (
|
|
.io_in_0_ready (_ll_arb_io_in_0_ready),
|
|
.io_in_0_valid (_div_io_resp_valid),
|
|
.io_in_0_bits_data (_div_io_resp_bits_data),
|
|
.io_in_0_bits_tag (_div_io_resp_bits_tag),
|
|
.io_out_ready (ll_arb_io_out_ready),
|
|
.io_out_valid (_ll_arb_io_out_valid),
|
|
.io_out_bits_data (_ll_arb_io_out_bits_data),
|
|
.io_out_bits_tag (_ll_arb_io_out_bits_tag)
|
|
);
|
|
PlusArgTimeout PlusArgTimeout (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_count (_csr_io_time[31:0])
|
|
);
|
|
assign io_imem_might_request = imem_might_request_reg;
|
|
assign io_imem_req_valid = ibuf_io_kill;
|
|
assign io_imem_req_bits_pc =
|
|
wb_xcpt | _csr_io_eret ? _csr_io_evec : _replay_wb_T ? wb_reg_pc : mem_npc;
|
|
assign io_imem_req_bits_speculative = ~take_pc_wb;
|
|
assign io_imem_btb_update_valid =
|
|
mem_reg_valid & ~take_pc_wb
|
|
& (ex_pc_valid
|
|
? mem_npc != ex_reg_pc
|
|
: ~(_ibuf_io_inst_0_valid | io_imem_resp_valid) | mem_npc != _ibuf_io_pc)
|
|
& (~(mem_ctrl_branch | mem_ctrl_jalr | mem_ctrl_jal) | mem_cfi_taken);
|
|
assign io_imem_bht_update_valid = mem_reg_valid & ~take_pc_wb;
|
|
assign io_imem_flush_icache = wb_reg_valid & wb_ctrl_fence_i & ~io_dmem_s2_nack;
|
|
assign io_dmem_req_valid = io_dmem_req_valid_0;
|
|
assign io_dmem_req_bits_addr =
|
|
{ex_rs_0[63:33] == 31'h0 | (&(ex_rs_0[63:33]))
|
|
? _alu_io_adder_out[33]
|
|
: ~(_alu_io_adder_out[32]),
|
|
_alu_io_adder_out[32:0]};
|
|
assign io_dmem_req_bits_tag = {1'h0, ex_reg_inst[11:7], ex_ctrl_fp};
|
|
assign io_dmem_req_bits_cmd = ex_ctrl_mem_cmd;
|
|
assign io_dmem_req_bits_size = ex_reg_mem_size;
|
|
assign io_dmem_req_bits_signed = ~(ex_reg_inst[14]);
|
|
assign io_dmem_s1_kill = killm_common | mem_ldst_xcpt | fpu_kill_mem;
|
|
assign io_dmem_s1_data_data = mem_ctrl_fp ? io_fpu_store_data : mem_reg_rs2;
|
|
assign io_ptw_status_debug = _csr_io_status_debug;
|
|
assign io_ptw_customCSRs_csrs_0_value = _csr_io_customCSRs_0_value;
|
|
assign io_fpu_inst = _ibuf_io_inst_0_bits_inst_bits;
|
|
assign io_fpu_fromint_data = ex_rs_0;
|
|
assign io_fpu_ll_resp_val = dmem_resp_valid & io_dmem_resp_bits_tag[0];
|
|
assign io_fpu_ll_resp_type = {1'h0, io_dmem_resp_bits_size};
|
|
assign io_fpu_ll_resp_tag = io_dmem_resp_bits_tag[5:1];
|
|
assign io_fpu_ll_resp_data = io_dmem_resp_bits_data_word_bypass;
|
|
assign io_fpu_valid = ~ctrl_killd & id_ctrl_fp;
|
|
assign io_fpu_killx = ctrl_killx;
|
|
assign io_fpu_killm = killm_common;
|
|
endmodule
|
|
|