onur
94 lines
3.5 KiB
Systemverilog
94 lines
3.5 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module TLBusBypassBar(
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input clock,
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reset,
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output auto_in_a_ready,
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input auto_in_a_valid,
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input [2:0] auto_in_a_bits_opcode,
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input [8:0] auto_in_a_bits_address,
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input [31:0] auto_in_a_bits_data,
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input auto_in_d_ready,
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output auto_in_d_valid,
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auto_in_d_bits_denied,
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output [31:0] auto_in_d_bits_data,
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output auto_in_d_bits_corrupt,
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input auto_out_1_a_ready,
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output auto_out_1_a_valid,
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output [2:0] auto_out_1_a_bits_opcode,
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output [8:0] auto_out_1_a_bits_address,
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output [31:0] auto_out_1_a_bits_data,
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output auto_out_1_d_ready,
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input auto_out_1_d_valid,
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input [2:0] auto_out_1_d_bits_opcode,
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input auto_out_1_d_bits_denied,
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input [31:0] auto_out_1_d_bits_data,
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input auto_out_1_d_bits_corrupt,
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auto_out_0_a_ready,
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output auto_out_0_a_valid,
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output [2:0] auto_out_0_a_bits_opcode,
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output auto_out_0_d_ready,
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input auto_out_0_d_valid,
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input [2:0] auto_out_0_d_bits_opcode,
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input auto_out_0_d_bits_denied,
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auto_out_0_d_bits_corrupt,
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io_bypass
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);
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reg in_reset;
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reg bypass_reg;
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wire bypass = in_reset ? io_bypass : bypass_reg;
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reg [1:0] flight;
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reg r_counter;
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reg r_counter_3;
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reg stall_counter;
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wire stall = bypass != io_bypass & ~stall_counter;
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wire nodeIn_a_ready = ~stall & (bypass ? auto_out_0_a_ready : auto_out_1_a_ready);
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wire nodeIn_d_valid = bypass ? auto_out_0_d_valid : auto_out_1_d_valid;
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wire [1:0] nodeIn_d_bits_opcode =
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bypass ? auto_out_0_d_bits_opcode[2:1] : auto_out_1_d_bits_opcode[2:1];
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always @(posedge clock) begin
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automatic logic r_3;
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automatic logic d_dec;
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automatic logic [1:0] _next_flight_T_10;
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r_3 = nodeIn_a_ready & auto_in_a_valid;
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d_dec = auto_in_d_ready & nodeIn_d_valid;
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_next_flight_T_10 =
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flight
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+ {1'h0,
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d_dec & ~r_counter_3 & nodeIn_d_bits_opcode[1] & ~(nodeIn_d_bits_opcode[0])}
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+ {1'h0, r_3 & ~r_counter} - {1'h0, d_dec};
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if (reset) begin
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in_reset <= 1'h1;
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flight <= 2'h0;
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r_counter <= 1'h0;
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r_counter_3 <= 1'h0;
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stall_counter <= 1'h0;
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end
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else begin
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in_reset <= 1'h0;
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flight <= _next_flight_T_10;
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r_counter <= (~r_3 | r_counter - 1'h1) & r_counter;
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r_counter_3 <= (~d_dec | r_counter_3 - 1'h1) & r_counter_3;
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stall_counter <= (~r_3 | stall_counter - 1'h1) & stall_counter;
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end
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if (in_reset | _next_flight_T_10 == 2'h0)
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bypass_reg <= io_bypass;
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end // always @(posedge)
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assign auto_in_a_ready = nodeIn_a_ready;
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assign auto_in_d_valid = nodeIn_d_valid;
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assign auto_in_d_bits_denied =
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bypass ? auto_out_0_d_bits_denied : auto_out_1_d_bits_denied;
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assign auto_in_d_bits_data = bypass ? 32'h0 : auto_out_1_d_bits_data;
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assign auto_in_d_bits_corrupt =
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bypass ? auto_out_0_d_bits_corrupt : auto_out_1_d_bits_corrupt;
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assign auto_out_1_a_valid = ~stall & auto_in_a_valid & ~bypass;
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assign auto_out_1_a_bits_opcode = auto_in_a_bits_opcode;
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assign auto_out_1_a_bits_address = auto_in_a_bits_address;
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assign auto_out_1_a_bits_data = auto_in_a_bits_data;
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assign auto_out_1_d_ready = auto_in_d_ready & ~bypass;
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assign auto_out_0_a_valid = ~stall & auto_in_a_valid & bypass;
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assign auto_out_0_a_bits_opcode = auto_in_a_bits_opcode;
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assign auto_out_0_d_ready = auto_in_d_ready & bypass;
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endmodule
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