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gps/hardware/generated/genesys2-soc-verilog/TLDebugModuleInner.sv
T
onur b4920d31e3 max2771 spi liens has been added.
2026-08-06 22:14:52 +03:00

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154 KiB
Systemverilog
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// Generated by CIRCT firtool-1.151.0
// Users can define 'PRINTF_COND' to add an extra gate to prints.
`ifndef PRINTF_COND_
`ifdef PRINTF_COND
`define PRINTF_COND_ (`PRINTF_COND)
`else // PRINTF_COND
`define PRINTF_COND_ 1
`endif // PRINTF_COND
`endif // not def PRINTF_COND_
module TLDebugModuleInner(
input clock,
reset,
auto_sb2tlOpt_out_a_ready,
output auto_sb2tlOpt_out_a_valid,
output [2:0] auto_sb2tlOpt_out_a_bits_opcode,
output [3:0] auto_sb2tlOpt_out_a_bits_size,
output [31:0] auto_sb2tlOpt_out_a_bits_address,
output [7:0] auto_sb2tlOpt_out_a_bits_data,
output auto_sb2tlOpt_out_d_ready,
input auto_sb2tlOpt_out_d_valid,
input [2:0] auto_sb2tlOpt_out_d_bits_opcode,
input [1:0] auto_sb2tlOpt_out_d_bits_param,
input [3:0] auto_sb2tlOpt_out_d_bits_size,
input auto_sb2tlOpt_out_d_bits_sink,
auto_sb2tlOpt_out_d_bits_denied,
input [7:0] auto_sb2tlOpt_out_d_bits_data,
input auto_sb2tlOpt_out_d_bits_corrupt,
output auto_tl_in_a_ready,
input auto_tl_in_a_valid,
input [2:0] auto_tl_in_a_bits_opcode,
input [1:0] auto_tl_in_a_bits_size,
input [5:0] auto_tl_in_a_bits_source,
input [11:0] auto_tl_in_a_bits_address,
input [7:0] auto_tl_in_a_bits_mask,
input [63:0] auto_tl_in_a_bits_data,
input auto_tl_in_d_ready,
output auto_tl_in_d_valid,
output [2:0] auto_tl_in_d_bits_opcode,
output [1:0] auto_tl_in_d_bits_size,
output [5:0] auto_tl_in_d_bits_source,
output [63:0] auto_tl_in_d_bits_data,
output auto_dmi_in_a_ready,
input auto_dmi_in_a_valid,
input [2:0] auto_dmi_in_a_bits_opcode,
input [1:0] auto_dmi_in_a_bits_size,
input auto_dmi_in_a_bits_source,
input [8:0] auto_dmi_in_a_bits_address,
input [3:0] auto_dmi_in_a_bits_mask,
input [31:0] auto_dmi_in_a_bits_data,
input auto_dmi_in_d_ready,
output auto_dmi_in_d_valid,
output [2:0] auto_dmi_in_d_bits_opcode,
output [1:0] auto_dmi_in_d_bits_size,
output auto_dmi_in_d_bits_source,
output [31:0] auto_dmi_in_d_bits_data,
input io_dmactive,
io_innerCtrl_valid,
io_innerCtrl_bits_resumereq,
input [9:0] io_innerCtrl_bits_hartsel,
input io_innerCtrl_bits_ackhavereset,
io_innerCtrl_bits_hrmask_0,
output io_hgDebugInt_0,
input io_hartIsInReset_0,
io_tl_clock,
io_tl_reset
);
wire goAbstract;
wire _GEN;
wire abstractCommandBusy;
wire out_woready_1_345;
wire out_woready_1_528;
wire hartGoingWrEn;
wire [9:0] hartGoingId;
wire out_woready_9;
wire out_woready_44;
wire out_woready_59;
wire out_woready_72;
wire out_woready_111;
wire out_woready_36;
wire out_woready_48;
wire out_woready_24;
wire out_woready_115;
wire out_woready_28;
wire out_woready_64;
wire out_woready_55;
wire out_woready_120;
wire out_woready_32;
wire out_woready_99;
wire out_woready_68;
wire out_woready_96;
wire out_woready_51;
wire out_woready_3;
wire out_woready_40;
wire _out_wofireMux_T_2;
wire out_roready_44;
wire out_roready_59;
wire out_roready_72;
wire out_roready_111;
wire out_roready_36;
wire out_roready_48;
wire out_roready_24;
wire out_roready_115;
wire out_roready_28;
wire out_roready_64;
wire out_roready_55;
wire out_roready_120;
wire out_roready_32;
wire out_roready_99;
wire out_roready_68;
wire out_roready_96;
wire out_roready_3;
wire out_roready_40;
wire _out_rofireMux_T_1;
wire out_backSel_61;
wire out_backSel_60;
wire out_backSel_57;
wire out_backSel_23;
wire out_backSel_22;
wire dmiProgramBufferWrEnMaybe_19;
wire dmiProgramBufferRdEn_19;
wire dmiProgramBufferWrEnMaybe_18;
wire dmiProgramBufferRdEn_18;
wire dmiProgramBufferWrEnMaybe_17;
wire dmiProgramBufferRdEn_17;
wire dmiProgramBufferWrEnMaybe_16;
wire dmiProgramBufferRdEn_16;
wire [31:0] COMMANDWrDataVal;
wire COMMANDWrEnMaybe;
wire dmiProgramBufferWrEnMaybe_35;
wire dmiProgramBufferRdEn_35;
wire dmiProgramBufferWrEnMaybe_34;
wire dmiProgramBufferRdEn_34;
wire dmiProgramBufferWrEnMaybe_33;
wire dmiProgramBufferRdEn_33;
wire dmiProgramBufferWrEnMaybe_32;
wire dmiProgramBufferRdEn_32;
wire dmiProgramBufferWrEnMaybe_51;
wire dmiProgramBufferRdEn_51;
wire dmiProgramBufferWrEnMaybe_50;
wire dmiProgramBufferRdEn_50;
wire dmiProgramBufferWrEnMaybe_49;
wire dmiProgramBufferRdEn_49;
wire dmiProgramBufferWrEnMaybe_48;
wire dmiProgramBufferRdEn_48;
wire dmiProgramBufferWrEnMaybe_11;
wire dmiProgramBufferRdEn_11;
wire dmiProgramBufferWrEnMaybe_10;
wire dmiProgramBufferRdEn_10;
wire dmiProgramBufferWrEnMaybe_9;
wire dmiProgramBufferRdEn_9;
wire dmiProgramBufferWrEnMaybe_8;
wire dmiProgramBufferRdEn_8;
wire dmiProgramBufferWrEnMaybe_3;
wire dmiProgramBufferRdEn_3;
wire dmiProgramBufferWrEnMaybe_2;
wire dmiProgramBufferRdEn_2;
wire dmiProgramBufferWrEnMaybe_1;
wire dmiProgramBufferRdEn_1;
wire dmiProgramBufferWrEnMaybe_0;
wire dmiProgramBufferRdEn_0;
wire dmiProgramBufferWrEnMaybe_55;
wire dmiProgramBufferRdEn_55;
wire dmiProgramBufferWrEnMaybe_54;
wire dmiProgramBufferRdEn_54;
wire dmiProgramBufferWrEnMaybe_53;
wire dmiProgramBufferRdEn_53;
wire dmiProgramBufferWrEnMaybe_52;
wire dmiProgramBufferRdEn_52;
wire dmiProgramBufferWrEnMaybe_7;
wire dmiProgramBufferRdEn_7;
wire dmiProgramBufferWrEnMaybe_6;
wire dmiProgramBufferRdEn_6;
wire dmiProgramBufferWrEnMaybe_5;
wire dmiProgramBufferRdEn_5;
wire dmiProgramBufferWrEnMaybe_4;
wire dmiProgramBufferRdEn_4;
wire dmiProgramBufferWrEnMaybe_27;
wire dmiProgramBufferRdEn_27;
wire dmiProgramBufferWrEnMaybe_26;
wire dmiProgramBufferRdEn_26;
wire dmiProgramBufferWrEnMaybe_25;
wire dmiProgramBufferRdEn_25;
wire dmiProgramBufferWrEnMaybe_24;
wire dmiProgramBufferRdEn_24;
wire anyAddressWrEn;
wire dmiProgramBufferWrEnMaybe_59;
wire dmiProgramBufferRdEn_59;
wire dmiProgramBufferWrEnMaybe_58;
wire dmiProgramBufferRdEn_58;
wire dmiProgramBufferWrEnMaybe_57;
wire dmiProgramBufferRdEn_57;
wire dmiProgramBufferWrEnMaybe_56;
wire dmiProgramBufferRdEn_56;
wire dmiProgramBufferWrEnMaybe_23;
wire dmiProgramBufferRdEn_23;
wire dmiProgramBufferWrEnMaybe_22;
wire dmiProgramBufferRdEn_22;
wire dmiProgramBufferWrEnMaybe_21;
wire dmiProgramBufferRdEn_21;
wire dmiProgramBufferWrEnMaybe_20;
wire dmiProgramBufferRdEn_20;
wire dmiProgramBufferWrEnMaybe_43;
wire dmiProgramBufferRdEn_43;
wire dmiProgramBufferWrEnMaybe_42;
wire dmiProgramBufferRdEn_42;
wire dmiProgramBufferWrEnMaybe_41;
wire dmiProgramBufferRdEn_41;
wire dmiProgramBufferWrEnMaybe_40;
wire dmiProgramBufferRdEn_40;
wire dmiProgramBufferWrEnMaybe_63;
wire dmiProgramBufferRdEn_63;
wire dmiProgramBufferWrEnMaybe_62;
wire dmiProgramBufferRdEn_62;
wire dmiProgramBufferWrEnMaybe_61;
wire dmiProgramBufferRdEn_61;
wire dmiProgramBufferWrEnMaybe_60;
wire dmiProgramBufferRdEn_60;
wire dmiAbstractDataWrEnMaybe_3;
wire dmiAbstractDataRdEn_3;
wire dmiAbstractDataWrEnMaybe_2;
wire dmiAbstractDataRdEn_2;
wire dmiAbstractDataWrEnMaybe_1;
wire dmiAbstractDataRdEn_1;
wire dmiAbstractDataWrEnMaybe_0;
wire dmiAbstractDataRdEn_0;
wire dmiProgramBufferWrEnMaybe_47;
wire dmiProgramBufferRdEn_47;
wire dmiProgramBufferWrEnMaybe_46;
wire dmiProgramBufferRdEn_46;
wire dmiProgramBufferWrEnMaybe_45;
wire dmiProgramBufferRdEn_45;
wire dmiProgramBufferWrEnMaybe_44;
wire dmiProgramBufferRdEn_44;
wire dmiProgramBufferWrEnMaybe_15;
wire dmiProgramBufferRdEn_15;
wire dmiProgramBufferWrEnMaybe_14;
wire dmiProgramBufferRdEn_14;
wire dmiProgramBufferWrEnMaybe_13;
wire dmiProgramBufferRdEn_13;
wire dmiProgramBufferWrEnMaybe_12;
wire dmiProgramBufferRdEn_12;
wire dmiProgramBufferWrEnMaybe_31;
wire dmiProgramBufferRdEn_31;
wire dmiProgramBufferWrEnMaybe_30;
wire dmiProgramBufferRdEn_30;
wire dmiProgramBufferWrEnMaybe_29;
wire dmiProgramBufferRdEn_29;
wire dmiProgramBufferWrEnMaybe_28;
wire dmiProgramBufferRdEn_28;
wire dmiProgramBufferWrEnMaybe_39;
wire dmiProgramBufferRdEn_39;
wire dmiProgramBufferWrEnMaybe_38;
wire dmiProgramBufferRdEn_38;
wire dmiProgramBufferWrEnMaybe_37;
wire dmiProgramBufferRdEn_37;
wire dmiProgramBufferWrEnMaybe_36;
wire dmiProgramBufferRdEn_36;
wire [31:0] SBDATAWrData_0;
wire SBDATAWrEn_0;
wire SBDATARdEn_0;
wire [31:0] SBDATAWrData_1;
wire dmiAbstractDataWrEnMaybe_7;
wire dmiAbstractDataRdEn_7;
wire dmiAbstractDataWrEnMaybe_6;
wire dmiAbstractDataRdEn_6;
wire dmiAbstractDataWrEnMaybe_5;
wire dmiAbstractDataRdEn_5;
wire dmiAbstractDataWrEnMaybe_4;
wire dmiAbstractDataRdEn_4;
wire [2:0] SBCSRdData_sberror;
wire sb2tlOpt_io_wrEn;
wire _hartIsInResetSync_0_debug_hartReset_0_io_q;
wire _sb2tlOpt_io_rdLegal;
wire _sb2tlOpt_io_wrLegal;
wire _sb2tlOpt_io_rdDone;
wire _sb2tlOpt_io_wrDone;
wire _sb2tlOpt_io_respError;
wire [7:0] _sb2tlOpt_io_dataOut;
wire _sb2tlOpt_io_rdLoad_0;
wire _sb2tlOpt_io_rdLoad_1;
wire _sb2tlOpt_io_rdLoad_2;
wire _sb2tlOpt_io_rdLoad_3;
wire _sb2tlOpt_io_rdLoad_4;
wire _sb2tlOpt_io_rdLoad_5;
wire _sb2tlOpt_io_rdLoad_6;
wire _sb2tlOpt_io_rdLoad_7;
wire [2:0] _sb2tlOpt_io_sbStateOut;
reg haltedBitRegs;
reg resumeReqRegs;
reg haveResetBitRegs;
wire _GEN_0 = |io_innerCtrl_bits_hartsel;
reg hrmaskReg_0;
reg hrDebugIntReg_0;
wire resumereq = io_innerCtrl_valid & io_innerCtrl_bits_resumereq;
wire [31:0] _GEN_1 = {31'h0, haltedBitRegs};
reg [2:0] ABSTRACTCSReg_cmderr;
reg [15:0] ABSTRACTAUTOReg_autoexecprogbuf;
reg [11:0] ABSTRACTAUTOReg_autoexecdata;
wire dmiAbstractDataAccessVec_0 =
dmiAbstractDataWrEnMaybe_0 | dmiAbstractDataRdEn_0;
wire dmiAbstractDataAccessVec_4 =
dmiAbstractDataWrEnMaybe_4 | dmiAbstractDataRdEn_4;
wire dmiProgramBufferAccessVec_0 =
dmiProgramBufferWrEnMaybe_0 | dmiProgramBufferRdEn_0;
wire dmiProgramBufferAccessVec_4 =
dmiProgramBufferWrEnMaybe_4 | dmiProgramBufferRdEn_4;
wire dmiProgramBufferAccessVec_8 =
dmiProgramBufferWrEnMaybe_8 | dmiProgramBufferRdEn_8;
wire dmiProgramBufferAccessVec_12 =
dmiProgramBufferWrEnMaybe_12 | dmiProgramBufferRdEn_12;
wire dmiProgramBufferAccessVec_16 =
dmiProgramBufferWrEnMaybe_16 | dmiProgramBufferRdEn_16;
wire dmiProgramBufferAccessVec_20 =
dmiProgramBufferWrEnMaybe_20 | dmiProgramBufferRdEn_20;
wire dmiProgramBufferAccessVec_24 =
dmiProgramBufferWrEnMaybe_24 | dmiProgramBufferRdEn_24;
wire dmiProgramBufferAccessVec_28 =
dmiProgramBufferWrEnMaybe_28 | dmiProgramBufferRdEn_28;
wire dmiProgramBufferAccessVec_32 =
dmiProgramBufferWrEnMaybe_32 | dmiProgramBufferRdEn_32;
wire dmiProgramBufferAccessVec_36 =
dmiProgramBufferWrEnMaybe_36 | dmiProgramBufferRdEn_36;
wire dmiProgramBufferAccessVec_40 =
dmiProgramBufferWrEnMaybe_40 | dmiProgramBufferRdEn_40;
wire dmiProgramBufferAccessVec_44 =
dmiProgramBufferWrEnMaybe_44 | dmiProgramBufferRdEn_44;
wire dmiProgramBufferAccessVec_48 =
dmiProgramBufferWrEnMaybe_48 | dmiProgramBufferRdEn_48;
wire dmiProgramBufferAccessVec_52 =
dmiProgramBufferWrEnMaybe_52 | dmiProgramBufferRdEn_52;
wire dmiProgramBufferAccessVec_56 =
dmiProgramBufferWrEnMaybe_56 | dmiProgramBufferRdEn_56;
wire dmiProgramBufferAccessVec_60 =
dmiProgramBufferWrEnMaybe_60 | dmiProgramBufferRdEn_60;
wire autoexec =
dmiAbstractDataAccessVec_0 & ABSTRACTAUTOReg_autoexecdata[0]
| dmiAbstractDataAccessVec_4 & ABSTRACTAUTOReg_autoexecdata[1]
| dmiProgramBufferAccessVec_0 & ABSTRACTAUTOReg_autoexecprogbuf[0]
| dmiProgramBufferAccessVec_4 & ABSTRACTAUTOReg_autoexecprogbuf[1]
| dmiProgramBufferAccessVec_8 & ABSTRACTAUTOReg_autoexecprogbuf[2]
| dmiProgramBufferAccessVec_12 & ABSTRACTAUTOReg_autoexecprogbuf[3]
| dmiProgramBufferAccessVec_16 & ABSTRACTAUTOReg_autoexecprogbuf[4]
| dmiProgramBufferAccessVec_20 & ABSTRACTAUTOReg_autoexecprogbuf[5]
| dmiProgramBufferAccessVec_24 & ABSTRACTAUTOReg_autoexecprogbuf[6]
| dmiProgramBufferAccessVec_28 & ABSTRACTAUTOReg_autoexecprogbuf[7]
| dmiProgramBufferAccessVec_32 & ABSTRACTAUTOReg_autoexecprogbuf[8]
| dmiProgramBufferAccessVec_36 & ABSTRACTAUTOReg_autoexecprogbuf[9]
| dmiProgramBufferAccessVec_40 & ABSTRACTAUTOReg_autoexecprogbuf[10]
| dmiProgramBufferAccessVec_44 & ABSTRACTAUTOReg_autoexecprogbuf[11]
| dmiProgramBufferAccessVec_48 & ABSTRACTAUTOReg_autoexecprogbuf[12]
| dmiProgramBufferAccessVec_52 & ABSTRACTAUTOReg_autoexecprogbuf[13]
| dmiProgramBufferAccessVec_56 & ABSTRACTAUTOReg_autoexecprogbuf[14]
| dmiProgramBufferAccessVec_60 & ABSTRACTAUTOReg_autoexecprogbuf[15];
reg [7:0] COMMANDReg_cmdtype;
reg [23:0] COMMANDReg_control;
wire COMMANDWrEn = COMMANDWrEnMaybe & ~_GEN;
reg [7:0] abstractDataMem_0;
reg [7:0] abstractDataMem_1;
reg [7:0] abstractDataMem_2;
reg [7:0] abstractDataMem_3;
reg [7:0] abstractDataMem_4;
reg [7:0] abstractDataMem_5;
reg [7:0] abstractDataMem_6;
reg [7:0] abstractDataMem_7;
reg [7:0] programBufferMem_0;
reg [7:0] programBufferMem_1;
reg [7:0] programBufferMem_2;
reg [7:0] programBufferMem_3;
reg [7:0] programBufferMem_4;
reg [7:0] programBufferMem_5;
reg [7:0] programBufferMem_6;
reg [7:0] programBufferMem_7;
reg [7:0] programBufferMem_8;
reg [7:0] programBufferMem_9;
reg [7:0] programBufferMem_10;
reg [7:0] programBufferMem_11;
reg [7:0] programBufferMem_12;
reg [7:0] programBufferMem_13;
reg [7:0] programBufferMem_14;
reg [7:0] programBufferMem_15;
reg [7:0] programBufferMem_16;
reg [7:0] programBufferMem_17;
reg [7:0] programBufferMem_18;
reg [7:0] programBufferMem_19;
reg [7:0] programBufferMem_20;
reg [7:0] programBufferMem_21;
reg [7:0] programBufferMem_22;
reg [7:0] programBufferMem_23;
reg [7:0] programBufferMem_24;
reg [7:0] programBufferMem_25;
reg [7:0] programBufferMem_26;
reg [7:0] programBufferMem_27;
reg [7:0] programBufferMem_28;
reg [7:0] programBufferMem_29;
reg [7:0] programBufferMem_30;
reg [7:0] programBufferMem_31;
reg [7:0] programBufferMem_32;
reg [7:0] programBufferMem_33;
reg [7:0] programBufferMem_34;
reg [7:0] programBufferMem_35;
reg [7:0] programBufferMem_36;
reg [7:0] programBufferMem_37;
reg [7:0] programBufferMem_38;
reg [7:0] programBufferMem_39;
reg [7:0] programBufferMem_40;
reg [7:0] programBufferMem_41;
reg [7:0] programBufferMem_42;
reg [7:0] programBufferMem_43;
reg [7:0] programBufferMem_44;
reg [7:0] programBufferMem_45;
reg [7:0] programBufferMem_46;
reg [7:0] programBufferMem_47;
reg [7:0] programBufferMem_48;
reg [7:0] programBufferMem_49;
reg [7:0] programBufferMem_50;
reg [7:0] programBufferMem_51;
reg [7:0] programBufferMem_52;
reg [7:0] programBufferMem_53;
reg [7:0] programBufferMem_54;
reg [7:0] programBufferMem_55;
reg [7:0] programBufferMem_56;
reg [7:0] programBufferMem_57;
reg [7:0] programBufferMem_58;
reg [7:0] programBufferMem_59;
reg [7:0] programBufferMem_60;
reg [7:0] programBufferMem_61;
reg [7:0] programBufferMem_62;
reg [7:0] programBufferMem_63;
reg SBCSFieldsReg_sbbusyerror;
reg SBCSFieldsReg_sbbusy;
reg SBCSFieldsReg_sbreadonaddr;
reg [2:0] SBCSFieldsReg_sbaccess;
reg SBCSFieldsReg_sbautoincrement;
reg SBCSFieldsReg_sbreadondata;
wire sbBusy = |_sb2tlOpt_io_sbStateOut;
reg [31:0] SBADDRESSFieldsReg_0;
wire _GEN_2 = |SBCSRdData_sberror;
reg [7:0] SBDATAFieldsReg_0_0;
reg [7:0] SBDATAFieldsReg_0_1;
reg [7:0] SBDATAFieldsReg_0_2;
reg [7:0] SBDATAFieldsReg_0_3;
reg [7:0] SBDATAFieldsReg_1_0;
reg [7:0] SBDATAFieldsReg_1_1;
reg [7:0] SBDATAFieldsReg_1_2;
reg [7:0] SBDATAFieldsReg_1_3;
wire tryRdEn =
anyAddressWrEn & SBCSFieldsReg_sbreadonaddr | SBDATARdEn_0
& SBCSFieldsReg_sbreadondata;
wire _sbAlignmentError_T_14 = SBCSFieldsReg_sbaccess == 3'h4;
wire sbAccessError =
_sbAlignmentError_T_14 | SBCSFieldsReg_sbaccess > 3'h4;
wire [3:0] compareAddr =
anyAddressWrEn ? auto_dmi_in_a_bits_data[3:0] : SBADDRESSFieldsReg_0[3:0];
wire sbAlignmentError =
SBCSFieldsReg_sbaccess == 3'h1 & compareAddr[0] | SBCSFieldsReg_sbaccess == 3'h2
& (|(compareAddr[1:0])) | SBCSFieldsReg_sbaccess == 3'h3 & (|(compareAddr[2:0]))
| _sbAlignmentError_T_14 & (|compareAddr);
assign sb2tlOpt_io_wrEn =
SBDATAWrEn_0 & ~SBCSFieldsReg_sbbusy & ~SBCSFieldsReg_sbbusyerror & ~_GEN_2
& ~sbAccessError & ~sbAlignmentError;
wire sb2tlOpt_io_rdEn =
tryRdEn & ~SBCSFieldsReg_sbbusy & ~SBCSFieldsReg_sbbusyerror & ~_GEN_2
& ~sbAccessError & ~sbAlignmentError;
reg sbErrorReg_0;
reg sbErrorReg_1;
reg sbErrorReg_2;
assign SBCSRdData_sberror = {sbErrorReg_2, sbErrorReg_1, sbErrorReg_0};
wire in_bits_read = auto_dmi_in_a_bits_opcode == 3'h4;
wire [7:0] _out_womask_T_119 = {8{auto_dmi_in_a_bits_mask[2]}};
wire [7:0] _out_womask_T_120 = {8{auto_dmi_in_a_bits_mask[3]}};
wire [31:0] out_backMask =
{_out_womask_T_120,
_out_womask_T_119,
{8{auto_dmi_in_a_bits_mask[1]}},
{8{auto_dmi_in_a_bits_mask[0]}}};
assign dmiAbstractDataRdEn_4 = out_roready_3 & auto_dmi_in_a_bits_mask[0];
assign dmiAbstractDataWrEnMaybe_4 = out_woready_3 & auto_dmi_in_a_bits_mask[0];
assign dmiAbstractDataRdEn_5 = out_roready_3 & auto_dmi_in_a_bits_mask[1];
assign dmiAbstractDataWrEnMaybe_5 = out_woready_3 & auto_dmi_in_a_bits_mask[1];
assign dmiAbstractDataRdEn_6 = out_roready_3 & auto_dmi_in_a_bits_mask[2];
assign dmiAbstractDataWrEnMaybe_6 = out_woready_3 & auto_dmi_in_a_bits_mask[2];
assign dmiAbstractDataRdEn_7 = out_roready_3 & auto_dmi_in_a_bits_mask[3];
assign dmiAbstractDataWrEnMaybe_7 = out_woready_3 & auto_dmi_in_a_bits_mask[3];
wire sberrorWrEn = out_woready_9 & auto_dmi_in_a_bits_mask[1];
wire SBDATAWrEn_1 =
_out_wofireMux_T_2 & out_backSel_61 & ~(auto_dmi_in_a_bits_address[8])
& (&out_backMask);
assign SBDATAWrData_1 = SBDATAWrEn_1 ? auto_dmi_in_a_bits_data : 32'h0;
assign SBDATARdEn_0 =
_out_rofireMux_T_1 & out_backSel_60 & ~(auto_dmi_in_a_bits_address[8])
& (|out_backMask);
assign SBDATAWrEn_0 =
_out_wofireMux_T_2 & out_backSel_60 & ~(auto_dmi_in_a_bits_address[8])
& (&out_backMask);
assign SBDATAWrData_0 = SBDATAWrEn_0 ? auto_dmi_in_a_bits_data : 32'h0;
assign dmiProgramBufferRdEn_36 = out_roready_24 & auto_dmi_in_a_bits_mask[0];
assign dmiProgramBufferWrEnMaybe_36 = out_woready_24 & auto_dmi_in_a_bits_mask[0];
assign dmiProgramBufferRdEn_37 = out_roready_24 & auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferWrEnMaybe_37 = out_woready_24 & auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferRdEn_38 = out_roready_24 & auto_dmi_in_a_bits_mask[2];
assign dmiProgramBufferWrEnMaybe_38 = out_woready_24 & auto_dmi_in_a_bits_mask[2];
assign dmiProgramBufferRdEn_39 = out_roready_24 & auto_dmi_in_a_bits_mask[3];
assign dmiProgramBufferWrEnMaybe_39 = out_woready_24 & auto_dmi_in_a_bits_mask[3];
assign dmiProgramBufferRdEn_28 = out_roready_28 & auto_dmi_in_a_bits_mask[0];
assign dmiProgramBufferWrEnMaybe_28 = out_woready_28 & auto_dmi_in_a_bits_mask[0];
assign dmiProgramBufferRdEn_29 = out_roready_28 & auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferWrEnMaybe_29 = out_woready_28 & auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferRdEn_30 = out_roready_28 & auto_dmi_in_a_bits_mask[2];
assign dmiProgramBufferWrEnMaybe_30 = out_woready_28 & auto_dmi_in_a_bits_mask[2];
assign dmiProgramBufferRdEn_31 = out_roready_28 & auto_dmi_in_a_bits_mask[3];
assign dmiProgramBufferWrEnMaybe_31 = out_woready_28 & auto_dmi_in_a_bits_mask[3];
assign dmiProgramBufferRdEn_12 = out_roready_32 & auto_dmi_in_a_bits_mask[0];
assign dmiProgramBufferWrEnMaybe_12 = out_woready_32 & auto_dmi_in_a_bits_mask[0];
assign dmiProgramBufferRdEn_13 = out_roready_32 & auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferWrEnMaybe_13 = out_woready_32 & auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferRdEn_14 = out_roready_32 & auto_dmi_in_a_bits_mask[2];
assign dmiProgramBufferWrEnMaybe_14 = out_woready_32 & auto_dmi_in_a_bits_mask[2];
assign dmiProgramBufferRdEn_15 = out_roready_32 & auto_dmi_in_a_bits_mask[3];
assign dmiProgramBufferWrEnMaybe_15 = out_woready_32 & auto_dmi_in_a_bits_mask[3];
assign dmiProgramBufferRdEn_44 = out_roready_36 & auto_dmi_in_a_bits_mask[0];
assign dmiProgramBufferWrEnMaybe_44 = out_woready_36 & auto_dmi_in_a_bits_mask[0];
assign dmiProgramBufferRdEn_45 = out_roready_36 & auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferWrEnMaybe_45 = out_woready_36 & auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferRdEn_46 = out_roready_36 & auto_dmi_in_a_bits_mask[2];
assign dmiProgramBufferWrEnMaybe_46 = out_woready_36 & auto_dmi_in_a_bits_mask[2];
assign dmiProgramBufferRdEn_47 = out_roready_36 & auto_dmi_in_a_bits_mask[3];
assign dmiProgramBufferWrEnMaybe_47 = out_woready_36 & auto_dmi_in_a_bits_mask[3];
assign dmiAbstractDataRdEn_0 = out_roready_40 & auto_dmi_in_a_bits_mask[0];
assign dmiAbstractDataWrEnMaybe_0 = out_woready_40 & auto_dmi_in_a_bits_mask[0];
assign dmiAbstractDataRdEn_1 = out_roready_40 & auto_dmi_in_a_bits_mask[1];
assign dmiAbstractDataWrEnMaybe_1 = out_woready_40 & auto_dmi_in_a_bits_mask[1];
assign dmiAbstractDataRdEn_2 = out_roready_40 & auto_dmi_in_a_bits_mask[2];
assign dmiAbstractDataWrEnMaybe_2 = out_woready_40 & auto_dmi_in_a_bits_mask[2];
assign dmiAbstractDataRdEn_3 = out_roready_40 & auto_dmi_in_a_bits_mask[3];
assign dmiAbstractDataWrEnMaybe_3 = out_woready_40 & auto_dmi_in_a_bits_mask[3];
assign dmiProgramBufferRdEn_60 = out_roready_44 & auto_dmi_in_a_bits_mask[0];
assign dmiProgramBufferWrEnMaybe_60 = out_woready_44 & auto_dmi_in_a_bits_mask[0];
assign dmiProgramBufferRdEn_61 = out_roready_44 & auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferWrEnMaybe_61 = out_woready_44 & auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferRdEn_62 = out_roready_44 & auto_dmi_in_a_bits_mask[2];
assign dmiProgramBufferWrEnMaybe_62 = out_woready_44 & auto_dmi_in_a_bits_mask[2];
assign dmiProgramBufferRdEn_63 = out_roready_44 & auto_dmi_in_a_bits_mask[3];
assign dmiProgramBufferWrEnMaybe_63 = out_woready_44 & auto_dmi_in_a_bits_mask[3];
assign dmiProgramBufferRdEn_40 = out_roready_48 & auto_dmi_in_a_bits_mask[0];
assign dmiProgramBufferWrEnMaybe_40 = out_woready_48 & auto_dmi_in_a_bits_mask[0];
assign dmiProgramBufferRdEn_41 = out_roready_48 & auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferWrEnMaybe_41 = out_woready_48 & auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferRdEn_42 = out_roready_48 & auto_dmi_in_a_bits_mask[2];
assign dmiProgramBufferWrEnMaybe_42 = out_woready_48 & auto_dmi_in_a_bits_mask[2];
assign dmiProgramBufferRdEn_43 = out_roready_48 & auto_dmi_in_a_bits_mask[3];
assign dmiProgramBufferWrEnMaybe_43 = out_woready_48 & auto_dmi_in_a_bits_mask[3];
wire autoexecdataWrEnMaybe = out_woready_51 & auto_dmi_in_a_bits_mask[0];
wire autoexecprogbufWrEnMaybe =
out_woready_51 & (&{_out_womask_T_120, _out_womask_T_119});
assign dmiProgramBufferRdEn_20 = out_roready_55 & auto_dmi_in_a_bits_mask[0];
assign dmiProgramBufferWrEnMaybe_20 = out_woready_55 & auto_dmi_in_a_bits_mask[0];
assign dmiProgramBufferRdEn_21 = out_roready_55 & auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferWrEnMaybe_21 = out_woready_55 & auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferRdEn_22 = out_roready_55 & auto_dmi_in_a_bits_mask[2];
assign dmiProgramBufferWrEnMaybe_22 = out_woready_55 & auto_dmi_in_a_bits_mask[2];
assign dmiProgramBufferRdEn_23 = out_roready_55 & auto_dmi_in_a_bits_mask[3];
assign dmiProgramBufferWrEnMaybe_23 = out_woready_55 & auto_dmi_in_a_bits_mask[3];
assign dmiProgramBufferRdEn_56 = out_roready_59 & auto_dmi_in_a_bits_mask[0];
assign dmiProgramBufferWrEnMaybe_56 = out_woready_59 & auto_dmi_in_a_bits_mask[0];
assign dmiProgramBufferRdEn_57 = out_roready_59 & auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferWrEnMaybe_57 = out_woready_59 & auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferRdEn_58 = out_roready_59 & auto_dmi_in_a_bits_mask[2];
assign dmiProgramBufferWrEnMaybe_58 = out_woready_59 & auto_dmi_in_a_bits_mask[2];
assign dmiProgramBufferRdEn_59 = out_roready_59 & auto_dmi_in_a_bits_mask[3];
assign dmiProgramBufferWrEnMaybe_59 = out_woready_59 & auto_dmi_in_a_bits_mask[3];
assign anyAddressWrEn =
_out_wofireMux_T_2 & out_backSel_57 & ~(auto_dmi_in_a_bits_address[8])
& (&out_backMask);
assign dmiProgramBufferRdEn_24 = out_roready_64 & auto_dmi_in_a_bits_mask[0];
assign dmiProgramBufferWrEnMaybe_24 = out_woready_64 & auto_dmi_in_a_bits_mask[0];
assign dmiProgramBufferRdEn_25 = out_roready_64 & auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferWrEnMaybe_25 = out_woready_64 & auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferRdEn_26 = out_roready_64 & auto_dmi_in_a_bits_mask[2];
assign dmiProgramBufferWrEnMaybe_26 = out_woready_64 & auto_dmi_in_a_bits_mask[2];
assign dmiProgramBufferRdEn_27 = out_roready_64 & auto_dmi_in_a_bits_mask[3];
assign dmiProgramBufferWrEnMaybe_27 = out_woready_64 & auto_dmi_in_a_bits_mask[3];
assign dmiProgramBufferRdEn_4 = out_roready_68 & auto_dmi_in_a_bits_mask[0];
assign dmiProgramBufferWrEnMaybe_4 = out_woready_68 & auto_dmi_in_a_bits_mask[0];
assign dmiProgramBufferRdEn_5 = out_roready_68 & auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferWrEnMaybe_5 = out_woready_68 & auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferRdEn_6 = out_roready_68 & auto_dmi_in_a_bits_mask[2];
assign dmiProgramBufferWrEnMaybe_6 = out_woready_68 & auto_dmi_in_a_bits_mask[2];
assign dmiProgramBufferRdEn_7 = out_roready_68 & auto_dmi_in_a_bits_mask[3];
assign dmiProgramBufferWrEnMaybe_7 = out_woready_68 & auto_dmi_in_a_bits_mask[3];
assign dmiProgramBufferRdEn_52 = out_roready_72 & auto_dmi_in_a_bits_mask[0];
assign dmiProgramBufferWrEnMaybe_52 = out_woready_72 & auto_dmi_in_a_bits_mask[0];
assign dmiProgramBufferRdEn_53 = out_roready_72 & auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferWrEnMaybe_53 = out_woready_72 & auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferRdEn_54 = out_roready_72 & auto_dmi_in_a_bits_mask[2];
assign dmiProgramBufferWrEnMaybe_54 = out_woready_72 & auto_dmi_in_a_bits_mask[2];
assign dmiProgramBufferRdEn_55 = out_roready_72 & auto_dmi_in_a_bits_mask[3];
assign dmiProgramBufferWrEnMaybe_55 = out_woready_72 & auto_dmi_in_a_bits_mask[3];
assign dmiProgramBufferRdEn_0 = out_roready_96 & auto_dmi_in_a_bits_mask[0];
assign dmiProgramBufferWrEnMaybe_0 = out_woready_96 & auto_dmi_in_a_bits_mask[0];
assign dmiProgramBufferRdEn_1 = out_roready_96 & auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferWrEnMaybe_1 = out_woready_96 & auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferRdEn_2 = out_roready_96 & auto_dmi_in_a_bits_mask[2];
assign dmiProgramBufferWrEnMaybe_2 = out_woready_96 & auto_dmi_in_a_bits_mask[2];
assign dmiProgramBufferRdEn_3 = out_roready_96 & auto_dmi_in_a_bits_mask[3];
assign dmiProgramBufferWrEnMaybe_3 = out_woready_96 & auto_dmi_in_a_bits_mask[3];
assign dmiProgramBufferRdEn_8 = out_roready_99 & auto_dmi_in_a_bits_mask[0];
assign dmiProgramBufferWrEnMaybe_8 = out_woready_99 & auto_dmi_in_a_bits_mask[0];
assign dmiProgramBufferRdEn_9 = out_roready_99 & auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferWrEnMaybe_9 = out_woready_99 & auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferRdEn_10 = out_roready_99 & auto_dmi_in_a_bits_mask[2];
assign dmiProgramBufferWrEnMaybe_10 = out_woready_99 & auto_dmi_in_a_bits_mask[2];
assign dmiProgramBufferRdEn_11 = out_roready_99 & auto_dmi_in_a_bits_mask[3];
assign dmiProgramBufferWrEnMaybe_11 = out_woready_99 & auto_dmi_in_a_bits_mask[3];
wire ABSTRACTCSWrEnMaybe =
_out_wofireMux_T_2 & out_backSel_22 & ~(auto_dmi_in_a_bits_address[8])
& auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferRdEn_48 = out_roready_111 & auto_dmi_in_a_bits_mask[0];
assign dmiProgramBufferWrEnMaybe_48 = out_woready_111 & auto_dmi_in_a_bits_mask[0];
assign dmiProgramBufferRdEn_49 = out_roready_111 & auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferWrEnMaybe_49 = out_woready_111 & auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferRdEn_50 = out_roready_111 & auto_dmi_in_a_bits_mask[2];
assign dmiProgramBufferWrEnMaybe_50 = out_woready_111 & auto_dmi_in_a_bits_mask[2];
assign dmiProgramBufferRdEn_51 = out_roready_111 & auto_dmi_in_a_bits_mask[3];
assign dmiProgramBufferWrEnMaybe_51 = out_woready_111 & auto_dmi_in_a_bits_mask[3];
assign dmiProgramBufferRdEn_32 = out_roready_115 & auto_dmi_in_a_bits_mask[0];
assign dmiProgramBufferWrEnMaybe_32 = out_woready_115 & auto_dmi_in_a_bits_mask[0];
assign dmiProgramBufferRdEn_33 = out_roready_115 & auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferWrEnMaybe_33 = out_woready_115 & auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferRdEn_34 = out_roready_115 & auto_dmi_in_a_bits_mask[2];
assign dmiProgramBufferWrEnMaybe_34 = out_woready_115 & auto_dmi_in_a_bits_mask[2];
assign dmiProgramBufferRdEn_35 = out_roready_115 & auto_dmi_in_a_bits_mask[3];
assign dmiProgramBufferWrEnMaybe_35 = out_woready_115 & auto_dmi_in_a_bits_mask[3];
assign COMMANDWrEnMaybe =
_out_wofireMux_T_2 & out_backSel_23 & ~(auto_dmi_in_a_bits_address[8])
& (&out_backMask);
assign COMMANDWrDataVal = COMMANDWrEnMaybe ? auto_dmi_in_a_bits_data : 32'h0;
assign dmiProgramBufferRdEn_16 = out_roready_120 & auto_dmi_in_a_bits_mask[0];
assign dmiProgramBufferWrEnMaybe_16 = out_woready_120 & auto_dmi_in_a_bits_mask[0];
assign dmiProgramBufferRdEn_17 = out_roready_120 & auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferWrEnMaybe_17 = out_woready_120 & auto_dmi_in_a_bits_mask[1];
assign dmiProgramBufferRdEn_18 = out_roready_120 & auto_dmi_in_a_bits_mask[2];
assign dmiProgramBufferWrEnMaybe_18 = out_woready_120 & auto_dmi_in_a_bits_mask[2];
assign dmiProgramBufferRdEn_19 = out_roready_120 & auto_dmi_in_a_bits_mask[3];
assign dmiProgramBufferWrEnMaybe_19 = out_woready_120 & auto_dmi_in_a_bits_mask[3];
wire [63:0] _out_backSel_T = 64'h1 << auto_dmi_in_a_bits_address[7:2];
assign out_backSel_22 = _out_backSel_T[22];
assign out_backSel_23 = _out_backSel_T[23];
assign out_backSel_57 = _out_backSel_T[57];
assign out_backSel_60 = _out_backSel_T[60];
assign out_backSel_61 = _out_backSel_T[61];
wire _out_wofireMux_T = auto_dmi_in_a_valid & auto_dmi_in_d_ready;
assign _out_rofireMux_T_1 = _out_wofireMux_T & in_bits_read;
assign out_roready_40 =
_out_rofireMux_T_1 & _out_backSel_T[4] & ~(auto_dmi_in_a_bits_address[8]);
assign out_roready_3 =
_out_rofireMux_T_1 & _out_backSel_T[5] & ~(auto_dmi_in_a_bits_address[8]);
assign out_roready_96 =
_out_rofireMux_T_1 & _out_backSel_T[32] & ~(auto_dmi_in_a_bits_address[8]);
assign out_roready_68 =
_out_rofireMux_T_1 & _out_backSel_T[33] & ~(auto_dmi_in_a_bits_address[8]);
assign out_roready_99 =
_out_rofireMux_T_1 & _out_backSel_T[34] & ~(auto_dmi_in_a_bits_address[8]);
assign out_roready_32 =
_out_rofireMux_T_1 & _out_backSel_T[35] & ~(auto_dmi_in_a_bits_address[8]);
assign out_roready_120 =
_out_rofireMux_T_1 & _out_backSel_T[36] & ~(auto_dmi_in_a_bits_address[8]);
assign out_roready_55 =
_out_rofireMux_T_1 & _out_backSel_T[37] & ~(auto_dmi_in_a_bits_address[8]);
assign out_roready_64 =
_out_rofireMux_T_1 & _out_backSel_T[38] & ~(auto_dmi_in_a_bits_address[8]);
assign out_roready_28 =
_out_rofireMux_T_1 & _out_backSel_T[39] & ~(auto_dmi_in_a_bits_address[8]);
assign out_roready_115 =
_out_rofireMux_T_1 & _out_backSel_T[40] & ~(auto_dmi_in_a_bits_address[8]);
assign out_roready_24 =
_out_rofireMux_T_1 & _out_backSel_T[41] & ~(auto_dmi_in_a_bits_address[8]);
assign out_roready_48 =
_out_rofireMux_T_1 & _out_backSel_T[42] & ~(auto_dmi_in_a_bits_address[8]);
assign out_roready_36 =
_out_rofireMux_T_1 & _out_backSel_T[43] & ~(auto_dmi_in_a_bits_address[8]);
assign out_roready_111 =
_out_rofireMux_T_1 & _out_backSel_T[44] & ~(auto_dmi_in_a_bits_address[8]);
assign out_roready_72 =
_out_rofireMux_T_1 & _out_backSel_T[45] & ~(auto_dmi_in_a_bits_address[8]);
assign out_roready_59 =
_out_rofireMux_T_1 & _out_backSel_T[46] & ~(auto_dmi_in_a_bits_address[8]);
assign out_roready_44 =
_out_rofireMux_T_1 & _out_backSel_T[47] & ~(auto_dmi_in_a_bits_address[8]);
assign _out_wofireMux_T_2 = _out_wofireMux_T & auto_dmi_in_a_bits_opcode != 3'h4;
assign out_woready_40 =
_out_wofireMux_T_2 & _out_backSel_T[4] & ~(auto_dmi_in_a_bits_address[8]);
assign out_woready_3 =
_out_wofireMux_T_2 & _out_backSel_T[5] & ~(auto_dmi_in_a_bits_address[8]);
assign out_woready_51 =
_out_wofireMux_T_2 & _out_backSel_T[24] & ~(auto_dmi_in_a_bits_address[8]);
assign out_woready_96 =
_out_wofireMux_T_2 & _out_backSel_T[32] & ~(auto_dmi_in_a_bits_address[8]);
assign out_woready_68 =
_out_wofireMux_T_2 & _out_backSel_T[33] & ~(auto_dmi_in_a_bits_address[8]);
assign out_woready_99 =
_out_wofireMux_T_2 & _out_backSel_T[34] & ~(auto_dmi_in_a_bits_address[8]);
assign out_woready_32 =
_out_wofireMux_T_2 & _out_backSel_T[35] & ~(auto_dmi_in_a_bits_address[8]);
assign out_woready_120 =
_out_wofireMux_T_2 & _out_backSel_T[36] & ~(auto_dmi_in_a_bits_address[8]);
assign out_woready_55 =
_out_wofireMux_T_2 & _out_backSel_T[37] & ~(auto_dmi_in_a_bits_address[8]);
assign out_woready_64 =
_out_wofireMux_T_2 & _out_backSel_T[38] & ~(auto_dmi_in_a_bits_address[8]);
assign out_woready_28 =
_out_wofireMux_T_2 & _out_backSel_T[39] & ~(auto_dmi_in_a_bits_address[8]);
assign out_woready_115 =
_out_wofireMux_T_2 & _out_backSel_T[40] & ~(auto_dmi_in_a_bits_address[8]);
assign out_woready_24 =
_out_wofireMux_T_2 & _out_backSel_T[41] & ~(auto_dmi_in_a_bits_address[8]);
assign out_woready_48 =
_out_wofireMux_T_2 & _out_backSel_T[42] & ~(auto_dmi_in_a_bits_address[8]);
assign out_woready_36 =
_out_wofireMux_T_2 & _out_backSel_T[43] & ~(auto_dmi_in_a_bits_address[8]);
assign out_woready_111 =
_out_wofireMux_T_2 & _out_backSel_T[44] & ~(auto_dmi_in_a_bits_address[8]);
assign out_woready_72 =
_out_wofireMux_T_2 & _out_backSel_T[45] & ~(auto_dmi_in_a_bits_address[8]);
assign out_woready_59 =
_out_wofireMux_T_2 & _out_backSel_T[46] & ~(auto_dmi_in_a_bits_address[8]);
assign out_woready_44 =
_out_wofireMux_T_2 & _out_backSel_T[47] & ~(auto_dmi_in_a_bits_address[8]);
assign out_woready_9 =
_out_wofireMux_T_2 & _out_backSel_T[56] & ~(auto_dmi_in_a_bits_address[8]);
wire _out_out_bits_data_T_28 = auto_dmi_in_a_bits_address[7:2] == 6'h0;
reg goReg;
wire _GEN_3 = |hartGoingId;
wire _GEN_4 = io_dmactive & ~goAbstract & hartGoingWrEn & ~reset;
reg [31:0] abstractGeneratedMem_0;
reg [31:0] abstractGeneratedMem_1;
wire [9:0] _out_womask_T_649 =
{{2{auto_tl_in_a_bits_mask[1]}}, {8{auto_tl_in_a_bits_mask[0]}}};
wire hartResumingWrEn = out_woready_1_345 & (&_out_womask_T_649);
wire [9:0] _out_womask_T_650 =
{{2{auto_tl_in_a_bits_mask[5]}}, {8{auto_tl_in_a_bits_mask[4]}}};
wire hartExceptionWrEn = out_woready_1_345 & (&_out_womask_T_650);
assign hartGoingId = auto_tl_in_a_bits_data[41:32];
wire hartHaltedWrEn = out_woready_1_528 & (&_out_womask_T_649);
assign hartGoingWrEn = out_woready_1_528 & (&_out_womask_T_650);
wire [255:0] _out_backSel_T_1 = 256'h1 << auto_tl_in_a_bits_address[10:3];
wire _out_wofireMux_T_262 =
auto_tl_in_a_valid & auto_tl_in_d_ready & auto_tl_in_a_bits_opcode != 3'h4;
assign out_woready_1_528 =
_out_wofireMux_T_262 & _out_backSel_T_1[32] & ~(auto_tl_in_a_bits_address[11]);
assign out_woready_1_345 =
_out_wofireMux_T_262 & _out_backSel_T_1[33] & ~(auto_tl_in_a_bits_address[11]);
wire out_woready_1_922 =
_out_wofireMux_T_262 & _out_backSel_T_1[104] & ~(auto_tl_in_a_bits_address[11]);
wire out_woready_1_510 =
_out_wofireMux_T_262 & _out_backSel_T_1[105] & ~(auto_tl_in_a_bits_address[11]);
wire out_woready_1_191 =
_out_wofireMux_T_262 & _out_backSel_T_1[106] & ~(auto_tl_in_a_bits_address[11]);
wire out_woready_1_1074 =
_out_wofireMux_T_262 & _out_backSel_T_1[107] & ~(auto_tl_in_a_bits_address[11]);
wire out_woready_1_722 =
_out_wofireMux_T_262 & _out_backSel_T_1[108] & ~(auto_tl_in_a_bits_address[11]);
wire out_woready_1_442 =
_out_wofireMux_T_262 & _out_backSel_T_1[109] & ~(auto_tl_in_a_bits_address[11]);
wire out_woready_1_111 =
_out_wofireMux_T_262 & _out_backSel_T_1[110] & ~(auto_tl_in_a_bits_address[11]);
wire out_woready_1_1146 =
_out_wofireMux_T_262 & _out_backSel_T_1[111] & ~(auto_tl_in_a_bits_address[11]);
wire out_woready_1_818 =
_out_wofireMux_T_262 & _out_backSel_T_1[112] & ~(auto_tl_in_a_bits_address[11]);
wire [255:0] _GEN_5 =
{{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{~(auto_tl_in_a_bits_address[11])},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{~(auto_tl_in_a_bits_address[11])},
{~(auto_tl_in_a_bits_address[11])},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{1'h1},
{auto_tl_in_a_bits_address[11]},
{auto_tl_in_a_bits_address[11]},
{auto_tl_in_a_bits_address[11]},
{auto_tl_in_a_bits_address[11]},
{auto_tl_in_a_bits_address[11]},
{auto_tl_in_a_bits_address[11]},
{auto_tl_in_a_bits_address[11]},
{auto_tl_in_a_bits_address[11]},
{auto_tl_in_a_bits_address[11]},
{auto_tl_in_a_bits_address[11]},
{auto_tl_in_a_bits_address[11]}};
wire [255:0][63:0] _GEN_6 =
{{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{{6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg,
6'h0,
resumeReqRegs,
goReg}},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{{abstractDataMem_7,
abstractDataMem_6,
abstractDataMem_5,
abstractDataMem_4,
abstractDataMem_3,
abstractDataMem_2,
abstractDataMem_1,
abstractDataMem_0}},
{{programBufferMem_63,
programBufferMem_62,
programBufferMem_61,
programBufferMem_60,
programBufferMem_59,
programBufferMem_58,
programBufferMem_57,
programBufferMem_56}},
{{programBufferMem_55,
programBufferMem_54,
programBufferMem_53,
programBufferMem_52,
programBufferMem_51,
programBufferMem_50,
programBufferMem_49,
programBufferMem_48}},
{{programBufferMem_47,
programBufferMem_46,
programBufferMem_45,
programBufferMem_44,
programBufferMem_43,
programBufferMem_42,
programBufferMem_41,
programBufferMem_40}},
{{programBufferMem_39,
programBufferMem_38,
programBufferMem_37,
programBufferMem_36,
programBufferMem_35,
programBufferMem_34,
programBufferMem_33,
programBufferMem_32}},
{{programBufferMem_31,
programBufferMem_30,
programBufferMem_29,
programBufferMem_28,
programBufferMem_27,
programBufferMem_26,
programBufferMem_25,
programBufferMem_24}},
{{programBufferMem_23,
programBufferMem_22,
programBufferMem_21,
programBufferMem_20,
programBufferMem_19,
programBufferMem_18,
programBufferMem_17,
programBufferMem_16}},
{{programBufferMem_15,
programBufferMem_14,
programBufferMem_13,
programBufferMem_12,
programBufferMem_11,
programBufferMem_10,
programBufferMem_9,
programBufferMem_8}},
{{programBufferMem_7,
programBufferMem_6,
programBufferMem_5,
programBufferMem_4,
programBufferMem_3,
programBufferMem_2,
programBufferMem_1,
programBufferMem_0}},
{{abstractGeneratedMem_1, abstractGeneratedMem_0}},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h380006F},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h0},
{64'h100073},
{64'h100026237B200073},
{64'h7B20247310802423},
{64'hF140247330000067},
{64'h100022237B202473},
{64'h4086300147413},
{64'hFE0408E300347413},
{64'h4004440310802023},
{64'hF14024737B241073},
{64'hFF0000F0440006F},
{64'h380006F00C0006F}};
reg [1:0] ctrlStateReg;
assign abstractCommandBusy = |ctrlStateReg;
assign _GEN = |ctrlStateReg;
wire _commandWrIsUnsupported_T = |(COMMANDWrDataVal[31:24]);
wire commandRegIsAccessRegister = COMMANDReg_cmdtype == 8'h0;
wire _GEN_7 =
~(COMMANDReg_control[17]) | (|(COMMANDReg_control[15:12]))
& COMMANDReg_control[15:0] < 16'h1020
& (COMMANDReg_control[22:20] == 3'h2 | COMMANDReg_control[22:20] == 3'h3);
wire commandRegIsUnsupported = ~commandRegIsAccessRegister | ~_GEN_7;
wire commandRegBadHaltResume =
commandRegIsAccessRegister & _GEN_7 & ~haltedBitRegs;
wire _regAccessRegisterCommand_T_1 = ABSTRACTCSReg_cmderr == 3'h0;
wire _GEN_8 =
COMMANDWrEn & ~_commandWrIsUnsupported_T & _regAccessRegisterCommand_T_1 | autoexec
& commandRegIsAccessRegister & _regAccessRegisterCommand_T_1;
wire _GEN_9 = ctrlStateReg == 2'h1;
wire _GEN_10 = commandRegIsUnsupported | commandRegBadHaltResume;
assign goAbstract = _GEN & _GEN_9 & ~_GEN_10;
wire _GEN_11 = _GEN & ctrlStateReg != 2'h1;
wire _GEN_12 = ctrlStateReg == 2'h2;
wire _GEN_13 = _GEN_11 & _GEN_12 & hartExceptionWrEn & ~reset;
wire _GEN_14 = _GEN_11 & ctrlStateReg != 2'h2 & (&ctrlStateReg) & ~reset;
wire _GEN_15 = ~io_dmactive | ~hartExceptionWrEn | _GEN_12;
`ifndef SYNTHESIS
always @(posedge clock) begin
if ((`PRINTF_COND_) & _GEN_4 & _GEN_3)
$fwrite(32'h80000002,
"Assertion failed: Unexpected 'GOING' hart.\n at Debug.scala:1505 assert(hartGoingId === 0.U, \"Unexpected 'GOING' hart.\")//Chisel3 #540 %%%%x, expected %%%%x\", hartGoingId, 0.U)\n");
if ((`PRINTF_COND_) & _GEN_13 & _GEN_3)
$fwrite(32'h80000002,
"Assertion failed: Unexpected 'EXCEPTION' hart\n at Debug.scala:1826 assert(hartExceptionId === 0.U, \"Unexpected 'EXCEPTION' hart\")//Chisel3 #540, %%%%x, expected %%%%x\", hartExceptionId, 0.U)\n");
if ((`PRINTF_COND_) & _GEN_14)
$fwrite(32'h80000002,
"Assertion failed: Should not be in custom state unless we need it.\n at Debug.scala:1831 assert(needCustom.B, \"Should not be in custom state unless we need it.\")\n");
if ((`PRINTF_COND_) & ~reset & ~_GEN_15)
$fwrite(32'h80000002,
"Assertion failed: Unexpected EXCEPTION write: should only get it in Debug Module EXEC state\n at Debug.scala:1844 assert ((!io.dmactive || !hartExceptionWrEn || ctrlStateReg === CtrlState(Exec)),\n");
end // always @(posedge)
`endif // not def SYNTHESIS
always @(posedge clock) begin
automatic logic _sbErrorReg_2_T_10 = SBDATAWrEn_0 | tryRdEn;
automatic logic _sbErrorReg_2_T_12 = _sb2tlOpt_io_rdDone | _sb2tlOpt_io_wrDone;
haltedBitRegs <=
io_dmactive & (hartHaltedWrEn | ~hartResumingWrEn & haltedBitRegs)
& ~_hartIsInResetSync_0_debug_hartReset_0_io_q;
resumeReqRegs <=
io_dmactive
& (resumereq
? (resumeReqRegs | ~_GEN_0) & ~_hartIsInResetSync_0_debug_hartReset_0_io_q
: ~hartResumingWrEn & resumeReqRegs
& ~_hartIsInResetSync_0_debug_hartReset_0_io_q);
haveResetBitRegs <=
io_dmactive
& (io_innerCtrl_valid & io_innerCtrl_bits_ackhavereset
? haveResetBitRegs & _GEN_0 | _hartIsInResetSync_0_debug_hartReset_0_io_q
: haveResetBitRegs | _hartIsInResetSync_0_debug_hartReset_0_io_q);
ABSTRACTCSReg_cmderr <=
io_dmactive
? (ABSTRACTCSWrEnMaybe & _GEN | autoexecdataWrEnMaybe & _GEN
| autoexecprogbufWrEnMaybe & _GEN | COMMANDWrEnMaybe & _GEN
| (dmiAbstractDataAccessVec_0 | dmiAbstractDataWrEnMaybe_1
| dmiAbstractDataRdEn_1 | dmiAbstractDataWrEnMaybe_2 | dmiAbstractDataRdEn_2
| dmiAbstractDataWrEnMaybe_3 | dmiAbstractDataRdEn_3
| dmiAbstractDataAccessVec_4 | dmiAbstractDataWrEnMaybe_5
| dmiAbstractDataRdEn_5 | dmiAbstractDataWrEnMaybe_6 | dmiAbstractDataRdEn_6
| dmiAbstractDataWrEnMaybe_7 | dmiAbstractDataRdEn_7) & _GEN
| (dmiProgramBufferAccessVec_0 | dmiProgramBufferWrEnMaybe_1
| dmiProgramBufferRdEn_1 | dmiProgramBufferWrEnMaybe_2
| dmiProgramBufferRdEn_2 | dmiProgramBufferWrEnMaybe_3
| dmiProgramBufferRdEn_3 | dmiProgramBufferAccessVec_4
| dmiProgramBufferWrEnMaybe_5 | dmiProgramBufferRdEn_5
| dmiProgramBufferWrEnMaybe_6 | dmiProgramBufferRdEn_6
| dmiProgramBufferWrEnMaybe_7 | dmiProgramBufferRdEn_7
| dmiProgramBufferAccessVec_8 | dmiProgramBufferWrEnMaybe_9
| dmiProgramBufferRdEn_9 | dmiProgramBufferWrEnMaybe_10
| dmiProgramBufferRdEn_10 | dmiProgramBufferWrEnMaybe_11
| dmiProgramBufferRdEn_11 | dmiProgramBufferAccessVec_12
| dmiProgramBufferWrEnMaybe_13 | dmiProgramBufferRdEn_13
| dmiProgramBufferWrEnMaybe_14 | dmiProgramBufferRdEn_14
| dmiProgramBufferWrEnMaybe_15 | dmiProgramBufferRdEn_15
| dmiProgramBufferAccessVec_16 | dmiProgramBufferWrEnMaybe_17
| dmiProgramBufferRdEn_17 | dmiProgramBufferWrEnMaybe_18
| dmiProgramBufferRdEn_18 | dmiProgramBufferWrEnMaybe_19
| dmiProgramBufferRdEn_19 | dmiProgramBufferAccessVec_20
| dmiProgramBufferWrEnMaybe_21 | dmiProgramBufferRdEn_21
| dmiProgramBufferWrEnMaybe_22 | dmiProgramBufferRdEn_22
| dmiProgramBufferWrEnMaybe_23 | dmiProgramBufferRdEn_23
| dmiProgramBufferAccessVec_24 | dmiProgramBufferWrEnMaybe_25
| dmiProgramBufferRdEn_25 | dmiProgramBufferWrEnMaybe_26
| dmiProgramBufferRdEn_26 | dmiProgramBufferWrEnMaybe_27
| dmiProgramBufferRdEn_27 | dmiProgramBufferAccessVec_28
| dmiProgramBufferWrEnMaybe_29 | dmiProgramBufferRdEn_29
| dmiProgramBufferWrEnMaybe_30 | dmiProgramBufferRdEn_30
| dmiProgramBufferWrEnMaybe_31 | dmiProgramBufferRdEn_31
| dmiProgramBufferAccessVec_32 | dmiProgramBufferWrEnMaybe_33
| dmiProgramBufferRdEn_33 | dmiProgramBufferWrEnMaybe_34
| dmiProgramBufferRdEn_34 | dmiProgramBufferWrEnMaybe_35
| dmiProgramBufferRdEn_35 | dmiProgramBufferAccessVec_36
| dmiProgramBufferWrEnMaybe_37 | dmiProgramBufferRdEn_37
| dmiProgramBufferWrEnMaybe_38 | dmiProgramBufferRdEn_38
| dmiProgramBufferWrEnMaybe_39 | dmiProgramBufferRdEn_39
| dmiProgramBufferAccessVec_40 | dmiProgramBufferWrEnMaybe_41
| dmiProgramBufferRdEn_41 | dmiProgramBufferWrEnMaybe_42
| dmiProgramBufferRdEn_42 | dmiProgramBufferWrEnMaybe_43
| dmiProgramBufferRdEn_43 | dmiProgramBufferAccessVec_44
| dmiProgramBufferWrEnMaybe_45 | dmiProgramBufferRdEn_45
| dmiProgramBufferWrEnMaybe_46 | dmiProgramBufferRdEn_46
| dmiProgramBufferWrEnMaybe_47 | dmiProgramBufferRdEn_47
| dmiProgramBufferAccessVec_48 | dmiProgramBufferWrEnMaybe_49
| dmiProgramBufferRdEn_49 | dmiProgramBufferWrEnMaybe_50
| dmiProgramBufferRdEn_50 | dmiProgramBufferWrEnMaybe_51
| dmiProgramBufferRdEn_51 | dmiProgramBufferAccessVec_52
| dmiProgramBufferWrEnMaybe_53 | dmiProgramBufferRdEn_53
| dmiProgramBufferWrEnMaybe_54 | dmiProgramBufferRdEn_54
| dmiProgramBufferWrEnMaybe_55 | dmiProgramBufferRdEn_55
| dmiProgramBufferAccessVec_56 | dmiProgramBufferWrEnMaybe_57
| dmiProgramBufferRdEn_57 | dmiProgramBufferWrEnMaybe_58
| dmiProgramBufferRdEn_58 | dmiProgramBufferWrEnMaybe_59
| dmiProgramBufferRdEn_59 | dmiProgramBufferAccessVec_60
| dmiProgramBufferWrEnMaybe_61 | dmiProgramBufferRdEn_61
| dmiProgramBufferWrEnMaybe_62 | dmiProgramBufferRdEn_62
| dmiProgramBufferWrEnMaybe_63 | dmiProgramBufferRdEn_63) & _GEN
? 3'h1
: ~(~_GEN | _GEN_9) & _GEN_12 & hartExceptionWrEn
? 3'h3
: (_GEN
? _GEN_9 & commandRegIsUnsupported
: ~_GEN_8
& (COMMANDWrEn & _commandWrIsUnsupported_T | autoexec
& commandRegIsUnsupported))
? 3'h2
: _GEN & _GEN_9 & ~commandRegIsUnsupported & commandRegBadHaltResume
? 3'h4
: ({3{~(ABSTRACTCSWrEnMaybe & ~_GEN)}}
| ~(auto_dmi_in_a_bits_data[10:8])) & ABSTRACTCSReg_cmderr)
: 3'h0;
if (io_dmactive) begin
if (autoexecprogbufWrEnMaybe & ~_GEN)
ABSTRACTAUTOReg_autoexecprogbuf <= auto_dmi_in_a_bits_data[31:16];
if (autoexecdataWrEnMaybe & ~_GEN)
ABSTRACTAUTOReg_autoexecdata <= {10'h0, auto_dmi_in_a_bits_data[1:0]};
if (COMMANDWrEn) begin
COMMANDReg_cmdtype <= COMMANDWrDataVal[31:24];
COMMANDReg_control <= COMMANDWrDataVal[23:0];
end
if (out_woready_1_818 & auto_tl_in_a_bits_mask[0])
abstractDataMem_0 <= auto_tl_in_a_bits_data[7:0];
else if (dmiAbstractDataWrEnMaybe_0 & ~_GEN)
abstractDataMem_0 <= auto_dmi_in_a_bits_data[7:0];
if (out_woready_1_818 & auto_tl_in_a_bits_mask[1])
abstractDataMem_1 <= auto_tl_in_a_bits_data[15:8];
else if (dmiAbstractDataWrEnMaybe_1 & ~_GEN)
abstractDataMem_1 <= auto_dmi_in_a_bits_data[15:8];
if (out_woready_1_818 & auto_tl_in_a_bits_mask[2])
abstractDataMem_2 <= auto_tl_in_a_bits_data[23:16];
else if (dmiAbstractDataWrEnMaybe_2 & ~_GEN)
abstractDataMem_2 <= auto_dmi_in_a_bits_data[23:16];
if (out_woready_1_818 & auto_tl_in_a_bits_mask[3])
abstractDataMem_3 <= auto_tl_in_a_bits_data[31:24];
else if (dmiAbstractDataWrEnMaybe_3 & ~_GEN)
abstractDataMem_3 <= auto_dmi_in_a_bits_data[31:24];
if (out_woready_1_818 & auto_tl_in_a_bits_mask[4])
abstractDataMem_4 <= auto_tl_in_a_bits_data[39:32];
else if (dmiAbstractDataWrEnMaybe_4 & ~_GEN)
abstractDataMem_4 <= auto_dmi_in_a_bits_data[7:0];
if (out_woready_1_818 & auto_tl_in_a_bits_mask[5])
abstractDataMem_5 <= auto_tl_in_a_bits_data[47:40];
else if (dmiAbstractDataWrEnMaybe_5 & ~_GEN)
abstractDataMem_5 <= auto_dmi_in_a_bits_data[15:8];
if (out_woready_1_818 & auto_tl_in_a_bits_mask[6])
abstractDataMem_6 <= auto_tl_in_a_bits_data[55:48];
else if (dmiAbstractDataWrEnMaybe_6 & ~_GEN)
abstractDataMem_6 <= auto_dmi_in_a_bits_data[23:16];
if (out_woready_1_818 & auto_tl_in_a_bits_mask[7])
abstractDataMem_7 <= auto_tl_in_a_bits_data[63:56];
else if (dmiAbstractDataWrEnMaybe_7 & ~_GEN)
abstractDataMem_7 <= auto_dmi_in_a_bits_data[31:24];
if (out_woready_1_922 & auto_tl_in_a_bits_mask[0])
programBufferMem_0 <= auto_tl_in_a_bits_data[7:0];
else if (dmiProgramBufferWrEnMaybe_0 & ~_GEN)
programBufferMem_0 <= auto_dmi_in_a_bits_data[7:0];
if (out_woready_1_922 & auto_tl_in_a_bits_mask[1])
programBufferMem_1 <= auto_tl_in_a_bits_data[15:8];
else if (dmiProgramBufferWrEnMaybe_1 & ~_GEN)
programBufferMem_1 <= auto_dmi_in_a_bits_data[15:8];
if (out_woready_1_922 & auto_tl_in_a_bits_mask[2])
programBufferMem_2 <= auto_tl_in_a_bits_data[23:16];
else if (dmiProgramBufferWrEnMaybe_2 & ~_GEN)
programBufferMem_2 <= auto_dmi_in_a_bits_data[23:16];
if (out_woready_1_922 & auto_tl_in_a_bits_mask[3])
programBufferMem_3 <= auto_tl_in_a_bits_data[31:24];
else if (dmiProgramBufferWrEnMaybe_3 & ~_GEN)
programBufferMem_3 <= auto_dmi_in_a_bits_data[31:24];
if (out_woready_1_922 & auto_tl_in_a_bits_mask[4])
programBufferMem_4 <= auto_tl_in_a_bits_data[39:32];
else if (dmiProgramBufferWrEnMaybe_4 & ~_GEN)
programBufferMem_4 <= auto_dmi_in_a_bits_data[7:0];
if (out_woready_1_922 & auto_tl_in_a_bits_mask[5])
programBufferMem_5 <= auto_tl_in_a_bits_data[47:40];
else if (dmiProgramBufferWrEnMaybe_5 & ~_GEN)
programBufferMem_5 <= auto_dmi_in_a_bits_data[15:8];
if (out_woready_1_922 & auto_tl_in_a_bits_mask[6])
programBufferMem_6 <= auto_tl_in_a_bits_data[55:48];
else if (dmiProgramBufferWrEnMaybe_6 & ~_GEN)
programBufferMem_6 <= auto_dmi_in_a_bits_data[23:16];
if (out_woready_1_922 & auto_tl_in_a_bits_mask[7])
programBufferMem_7 <= auto_tl_in_a_bits_data[63:56];
else if (dmiProgramBufferWrEnMaybe_7 & ~_GEN)
programBufferMem_7 <= auto_dmi_in_a_bits_data[31:24];
if (out_woready_1_510 & auto_tl_in_a_bits_mask[0])
programBufferMem_8 <= auto_tl_in_a_bits_data[7:0];
else if (dmiProgramBufferWrEnMaybe_8 & ~_GEN)
programBufferMem_8 <= auto_dmi_in_a_bits_data[7:0];
if (out_woready_1_510 & auto_tl_in_a_bits_mask[1])
programBufferMem_9 <= auto_tl_in_a_bits_data[15:8];
else if (dmiProgramBufferWrEnMaybe_9 & ~_GEN)
programBufferMem_9 <= auto_dmi_in_a_bits_data[15:8];
if (out_woready_1_510 & auto_tl_in_a_bits_mask[2])
programBufferMem_10 <= auto_tl_in_a_bits_data[23:16];
else if (dmiProgramBufferWrEnMaybe_10 & ~_GEN)
programBufferMem_10 <= auto_dmi_in_a_bits_data[23:16];
if (out_woready_1_510 & auto_tl_in_a_bits_mask[3])
programBufferMem_11 <= auto_tl_in_a_bits_data[31:24];
else if (dmiProgramBufferWrEnMaybe_11 & ~_GEN)
programBufferMem_11 <= auto_dmi_in_a_bits_data[31:24];
if (out_woready_1_510 & auto_tl_in_a_bits_mask[4])
programBufferMem_12 <= auto_tl_in_a_bits_data[39:32];
else if (dmiProgramBufferWrEnMaybe_12 & ~_GEN)
programBufferMem_12 <= auto_dmi_in_a_bits_data[7:0];
if (out_woready_1_510 & auto_tl_in_a_bits_mask[5])
programBufferMem_13 <= auto_tl_in_a_bits_data[47:40];
else if (dmiProgramBufferWrEnMaybe_13 & ~_GEN)
programBufferMem_13 <= auto_dmi_in_a_bits_data[15:8];
if (out_woready_1_510 & auto_tl_in_a_bits_mask[6])
programBufferMem_14 <= auto_tl_in_a_bits_data[55:48];
else if (dmiProgramBufferWrEnMaybe_14 & ~_GEN)
programBufferMem_14 <= auto_dmi_in_a_bits_data[23:16];
if (out_woready_1_510 & auto_tl_in_a_bits_mask[7])
programBufferMem_15 <= auto_tl_in_a_bits_data[63:56];
else if (dmiProgramBufferWrEnMaybe_15 & ~_GEN)
programBufferMem_15 <= auto_dmi_in_a_bits_data[31:24];
if (out_woready_1_191 & auto_tl_in_a_bits_mask[0])
programBufferMem_16 <= auto_tl_in_a_bits_data[7:0];
else if (dmiProgramBufferWrEnMaybe_16 & ~_GEN)
programBufferMem_16 <= auto_dmi_in_a_bits_data[7:0];
if (out_woready_1_191 & auto_tl_in_a_bits_mask[1])
programBufferMem_17 <= auto_tl_in_a_bits_data[15:8];
else if (dmiProgramBufferWrEnMaybe_17 & ~_GEN)
programBufferMem_17 <= auto_dmi_in_a_bits_data[15:8];
if (out_woready_1_191 & auto_tl_in_a_bits_mask[2])
programBufferMem_18 <= auto_tl_in_a_bits_data[23:16];
else if (dmiProgramBufferWrEnMaybe_18 & ~_GEN)
programBufferMem_18 <= auto_dmi_in_a_bits_data[23:16];
if (out_woready_1_191 & auto_tl_in_a_bits_mask[3])
programBufferMem_19 <= auto_tl_in_a_bits_data[31:24];
else if (dmiProgramBufferWrEnMaybe_19 & ~_GEN)
programBufferMem_19 <= auto_dmi_in_a_bits_data[31:24];
if (out_woready_1_191 & auto_tl_in_a_bits_mask[4])
programBufferMem_20 <= auto_tl_in_a_bits_data[39:32];
else if (dmiProgramBufferWrEnMaybe_20 & ~_GEN)
programBufferMem_20 <= auto_dmi_in_a_bits_data[7:0];
if (out_woready_1_191 & auto_tl_in_a_bits_mask[5])
programBufferMem_21 <= auto_tl_in_a_bits_data[47:40];
else if (dmiProgramBufferWrEnMaybe_21 & ~_GEN)
programBufferMem_21 <= auto_dmi_in_a_bits_data[15:8];
if (out_woready_1_191 & auto_tl_in_a_bits_mask[6])
programBufferMem_22 <= auto_tl_in_a_bits_data[55:48];
else if (dmiProgramBufferWrEnMaybe_22 & ~_GEN)
programBufferMem_22 <= auto_dmi_in_a_bits_data[23:16];
if (out_woready_1_191 & auto_tl_in_a_bits_mask[7])
programBufferMem_23 <= auto_tl_in_a_bits_data[63:56];
else if (dmiProgramBufferWrEnMaybe_23 & ~_GEN)
programBufferMem_23 <= auto_dmi_in_a_bits_data[31:24];
if (out_woready_1_1074 & auto_tl_in_a_bits_mask[0])
programBufferMem_24 <= auto_tl_in_a_bits_data[7:0];
else if (dmiProgramBufferWrEnMaybe_24 & ~_GEN)
programBufferMem_24 <= auto_dmi_in_a_bits_data[7:0];
if (out_woready_1_1074 & auto_tl_in_a_bits_mask[1])
programBufferMem_25 <= auto_tl_in_a_bits_data[15:8];
else if (dmiProgramBufferWrEnMaybe_25 & ~_GEN)
programBufferMem_25 <= auto_dmi_in_a_bits_data[15:8];
if (out_woready_1_1074 & auto_tl_in_a_bits_mask[2])
programBufferMem_26 <= auto_tl_in_a_bits_data[23:16];
else if (dmiProgramBufferWrEnMaybe_26 & ~_GEN)
programBufferMem_26 <= auto_dmi_in_a_bits_data[23:16];
if (out_woready_1_1074 & auto_tl_in_a_bits_mask[3])
programBufferMem_27 <= auto_tl_in_a_bits_data[31:24];
else if (dmiProgramBufferWrEnMaybe_27 & ~_GEN)
programBufferMem_27 <= auto_dmi_in_a_bits_data[31:24];
if (out_woready_1_1074 & auto_tl_in_a_bits_mask[4])
programBufferMem_28 <= auto_tl_in_a_bits_data[39:32];
else if (dmiProgramBufferWrEnMaybe_28 & ~_GEN)
programBufferMem_28 <= auto_dmi_in_a_bits_data[7:0];
if (out_woready_1_1074 & auto_tl_in_a_bits_mask[5])
programBufferMem_29 <= auto_tl_in_a_bits_data[47:40];
else if (dmiProgramBufferWrEnMaybe_29 & ~_GEN)
programBufferMem_29 <= auto_dmi_in_a_bits_data[15:8];
if (out_woready_1_1074 & auto_tl_in_a_bits_mask[6])
programBufferMem_30 <= auto_tl_in_a_bits_data[55:48];
else if (dmiProgramBufferWrEnMaybe_30 & ~_GEN)
programBufferMem_30 <= auto_dmi_in_a_bits_data[23:16];
if (out_woready_1_1074 & auto_tl_in_a_bits_mask[7])
programBufferMem_31 <= auto_tl_in_a_bits_data[63:56];
else if (dmiProgramBufferWrEnMaybe_31 & ~_GEN)
programBufferMem_31 <= auto_dmi_in_a_bits_data[31:24];
if (out_woready_1_722 & auto_tl_in_a_bits_mask[0])
programBufferMem_32 <= auto_tl_in_a_bits_data[7:0];
else if (dmiProgramBufferWrEnMaybe_32 & ~_GEN)
programBufferMem_32 <= auto_dmi_in_a_bits_data[7:0];
if (out_woready_1_722 & auto_tl_in_a_bits_mask[1])
programBufferMem_33 <= auto_tl_in_a_bits_data[15:8];
else if (dmiProgramBufferWrEnMaybe_33 & ~_GEN)
programBufferMem_33 <= auto_dmi_in_a_bits_data[15:8];
if (out_woready_1_722 & auto_tl_in_a_bits_mask[2])
programBufferMem_34 <= auto_tl_in_a_bits_data[23:16];
else if (dmiProgramBufferWrEnMaybe_34 & ~_GEN)
programBufferMem_34 <= auto_dmi_in_a_bits_data[23:16];
if (out_woready_1_722 & auto_tl_in_a_bits_mask[3])
programBufferMem_35 <= auto_tl_in_a_bits_data[31:24];
else if (dmiProgramBufferWrEnMaybe_35 & ~_GEN)
programBufferMem_35 <= auto_dmi_in_a_bits_data[31:24];
if (out_woready_1_722 & auto_tl_in_a_bits_mask[4])
programBufferMem_36 <= auto_tl_in_a_bits_data[39:32];
else if (dmiProgramBufferWrEnMaybe_36 & ~_GEN)
programBufferMem_36 <= auto_dmi_in_a_bits_data[7:0];
if (out_woready_1_722 & auto_tl_in_a_bits_mask[5])
programBufferMem_37 <= auto_tl_in_a_bits_data[47:40];
else if (dmiProgramBufferWrEnMaybe_37 & ~_GEN)
programBufferMem_37 <= auto_dmi_in_a_bits_data[15:8];
if (out_woready_1_722 & auto_tl_in_a_bits_mask[6])
programBufferMem_38 <= auto_tl_in_a_bits_data[55:48];
else if (dmiProgramBufferWrEnMaybe_38 & ~_GEN)
programBufferMem_38 <= auto_dmi_in_a_bits_data[23:16];
if (out_woready_1_722 & auto_tl_in_a_bits_mask[7])
programBufferMem_39 <= auto_tl_in_a_bits_data[63:56];
else if (dmiProgramBufferWrEnMaybe_39 & ~_GEN)
programBufferMem_39 <= auto_dmi_in_a_bits_data[31:24];
if (out_woready_1_442 & auto_tl_in_a_bits_mask[0])
programBufferMem_40 <= auto_tl_in_a_bits_data[7:0];
else if (dmiProgramBufferWrEnMaybe_40 & ~_GEN)
programBufferMem_40 <= auto_dmi_in_a_bits_data[7:0];
if (out_woready_1_442 & auto_tl_in_a_bits_mask[1])
programBufferMem_41 <= auto_tl_in_a_bits_data[15:8];
else if (dmiProgramBufferWrEnMaybe_41 & ~_GEN)
programBufferMem_41 <= auto_dmi_in_a_bits_data[15:8];
if (out_woready_1_442 & auto_tl_in_a_bits_mask[2])
programBufferMem_42 <= auto_tl_in_a_bits_data[23:16];
else if (dmiProgramBufferWrEnMaybe_42 & ~_GEN)
programBufferMem_42 <= auto_dmi_in_a_bits_data[23:16];
if (out_woready_1_442 & auto_tl_in_a_bits_mask[3])
programBufferMem_43 <= auto_tl_in_a_bits_data[31:24];
else if (dmiProgramBufferWrEnMaybe_43 & ~_GEN)
programBufferMem_43 <= auto_dmi_in_a_bits_data[31:24];
if (out_woready_1_442 & auto_tl_in_a_bits_mask[4])
programBufferMem_44 <= auto_tl_in_a_bits_data[39:32];
else if (dmiProgramBufferWrEnMaybe_44 & ~_GEN)
programBufferMem_44 <= auto_dmi_in_a_bits_data[7:0];
if (out_woready_1_442 & auto_tl_in_a_bits_mask[5])
programBufferMem_45 <= auto_tl_in_a_bits_data[47:40];
else if (dmiProgramBufferWrEnMaybe_45 & ~_GEN)
programBufferMem_45 <= auto_dmi_in_a_bits_data[15:8];
if (out_woready_1_442 & auto_tl_in_a_bits_mask[6])
programBufferMem_46 <= auto_tl_in_a_bits_data[55:48];
else if (dmiProgramBufferWrEnMaybe_46 & ~_GEN)
programBufferMem_46 <= auto_dmi_in_a_bits_data[23:16];
if (out_woready_1_442 & auto_tl_in_a_bits_mask[7])
programBufferMem_47 <= auto_tl_in_a_bits_data[63:56];
else if (dmiProgramBufferWrEnMaybe_47 & ~_GEN)
programBufferMem_47 <= auto_dmi_in_a_bits_data[31:24];
if (out_woready_1_111 & auto_tl_in_a_bits_mask[0])
programBufferMem_48 <= auto_tl_in_a_bits_data[7:0];
else if (dmiProgramBufferWrEnMaybe_48 & ~_GEN)
programBufferMem_48 <= auto_dmi_in_a_bits_data[7:0];
if (out_woready_1_111 & auto_tl_in_a_bits_mask[1])
programBufferMem_49 <= auto_tl_in_a_bits_data[15:8];
else if (dmiProgramBufferWrEnMaybe_49 & ~_GEN)
programBufferMem_49 <= auto_dmi_in_a_bits_data[15:8];
if (out_woready_1_111 & auto_tl_in_a_bits_mask[2])
programBufferMem_50 <= auto_tl_in_a_bits_data[23:16];
else if (dmiProgramBufferWrEnMaybe_50 & ~_GEN)
programBufferMem_50 <= auto_dmi_in_a_bits_data[23:16];
if (out_woready_1_111 & auto_tl_in_a_bits_mask[3])
programBufferMem_51 <= auto_tl_in_a_bits_data[31:24];
else if (dmiProgramBufferWrEnMaybe_51 & ~_GEN)
programBufferMem_51 <= auto_dmi_in_a_bits_data[31:24];
if (out_woready_1_111 & auto_tl_in_a_bits_mask[4])
programBufferMem_52 <= auto_tl_in_a_bits_data[39:32];
else if (dmiProgramBufferWrEnMaybe_52 & ~_GEN)
programBufferMem_52 <= auto_dmi_in_a_bits_data[7:0];
if (out_woready_1_111 & auto_tl_in_a_bits_mask[5])
programBufferMem_53 <= auto_tl_in_a_bits_data[47:40];
else if (dmiProgramBufferWrEnMaybe_53 & ~_GEN)
programBufferMem_53 <= auto_dmi_in_a_bits_data[15:8];
if (out_woready_1_111 & auto_tl_in_a_bits_mask[6])
programBufferMem_54 <= auto_tl_in_a_bits_data[55:48];
else if (dmiProgramBufferWrEnMaybe_54 & ~_GEN)
programBufferMem_54 <= auto_dmi_in_a_bits_data[23:16];
if (out_woready_1_111 & auto_tl_in_a_bits_mask[7])
programBufferMem_55 <= auto_tl_in_a_bits_data[63:56];
else if (dmiProgramBufferWrEnMaybe_55 & ~_GEN)
programBufferMem_55 <= auto_dmi_in_a_bits_data[31:24];
if (out_woready_1_1146 & auto_tl_in_a_bits_mask[0])
programBufferMem_56 <= auto_tl_in_a_bits_data[7:0];
else if (dmiProgramBufferWrEnMaybe_56 & ~_GEN)
programBufferMem_56 <= auto_dmi_in_a_bits_data[7:0];
if (out_woready_1_1146 & auto_tl_in_a_bits_mask[1])
programBufferMem_57 <= auto_tl_in_a_bits_data[15:8];
else if (dmiProgramBufferWrEnMaybe_57 & ~_GEN)
programBufferMem_57 <= auto_dmi_in_a_bits_data[15:8];
if (out_woready_1_1146 & auto_tl_in_a_bits_mask[2])
programBufferMem_58 <= auto_tl_in_a_bits_data[23:16];
else if (dmiProgramBufferWrEnMaybe_58 & ~_GEN)
programBufferMem_58 <= auto_dmi_in_a_bits_data[23:16];
if (out_woready_1_1146 & auto_tl_in_a_bits_mask[3])
programBufferMem_59 <= auto_tl_in_a_bits_data[31:24];
else if (dmiProgramBufferWrEnMaybe_59 & ~_GEN)
programBufferMem_59 <= auto_dmi_in_a_bits_data[31:24];
if (out_woready_1_1146 & auto_tl_in_a_bits_mask[4])
programBufferMem_60 <= auto_tl_in_a_bits_data[39:32];
else if (dmiProgramBufferWrEnMaybe_60 & ~_GEN)
programBufferMem_60 <= auto_dmi_in_a_bits_data[7:0];
if (out_woready_1_1146 & auto_tl_in_a_bits_mask[5])
programBufferMem_61 <= auto_tl_in_a_bits_data[47:40];
else if (dmiProgramBufferWrEnMaybe_61 & ~_GEN)
programBufferMem_61 <= auto_dmi_in_a_bits_data[15:8];
if (out_woready_1_1146 & auto_tl_in_a_bits_mask[6])
programBufferMem_62 <= auto_tl_in_a_bits_data[55:48];
else if (dmiProgramBufferWrEnMaybe_62 & ~_GEN)
programBufferMem_62 <= auto_dmi_in_a_bits_data[23:16];
if (out_woready_1_1146 & auto_tl_in_a_bits_mask[7])
programBufferMem_63 <= auto_tl_in_a_bits_data[63:56];
else if (dmiProgramBufferWrEnMaybe_63 & ~_GEN)
programBufferMem_63 <= auto_dmi_in_a_bits_data[31:24];
if (out_woready_9 & auto_dmi_in_a_bits_mask[2])
SBCSFieldsReg_sbaccess <= auto_dmi_in_a_bits_data[19:17];
if (anyAddressWrEn & ~_GEN_2 & ~SBCSFieldsReg_sbbusy & ~SBCSFieldsReg_sbbusyerror)
SBADDRESSFieldsReg_0 <= anyAddressWrEn ? auto_dmi_in_a_bits_data : 32'h0;
else if ((_sb2tlOpt_io_rdDone | _sb2tlOpt_io_wrDone)
& SBCSFieldsReg_sbautoincrement)
SBADDRESSFieldsReg_0 <=
SBADDRESSFieldsReg_0 + {24'h0, 8'h1 << SBCSFieldsReg_sbaccess};
if (SBDATAWrEn_0 & ~SBCSFieldsReg_sbbusy & ~SBCSFieldsReg_sbbusyerror & ~_GEN_2)
SBDATAFieldsReg_0_0 <= SBDATAWrData_0[7:0];
else if (_sb2tlOpt_io_rdLoad_0)
SBDATAFieldsReg_0_0 <= _sb2tlOpt_io_dataOut;
if (SBDATAWrEn_0 & ~SBCSFieldsReg_sbbusy & ~SBCSFieldsReg_sbbusyerror & ~_GEN_2)
SBDATAFieldsReg_0_1 <= SBDATAWrData_0[15:8];
else if (_sb2tlOpt_io_rdLoad_1)
SBDATAFieldsReg_0_1 <= _sb2tlOpt_io_dataOut;
if (SBDATAWrEn_0 & ~SBCSFieldsReg_sbbusy & ~SBCSFieldsReg_sbbusyerror & ~_GEN_2)
SBDATAFieldsReg_0_2 <= SBDATAWrData_0[23:16];
else if (_sb2tlOpt_io_rdLoad_2)
SBDATAFieldsReg_0_2 <= _sb2tlOpt_io_dataOut;
if (SBDATAWrEn_0 & ~SBCSFieldsReg_sbbusy & ~SBCSFieldsReg_sbbusyerror & ~_GEN_2)
SBDATAFieldsReg_0_3 <= SBDATAWrData_0[31:24];
else if (_sb2tlOpt_io_rdLoad_3)
SBDATAFieldsReg_0_3 <= _sb2tlOpt_io_dataOut;
if (SBDATAWrEn_1 & ~SBCSFieldsReg_sbbusy & ~SBCSFieldsReg_sbbusyerror & ~_GEN_2)
SBDATAFieldsReg_1_0 <= SBDATAWrData_1[7:0];
else if (_sb2tlOpt_io_rdLoad_4)
SBDATAFieldsReg_1_0 <= _sb2tlOpt_io_dataOut;
if (SBDATAWrEn_1 & ~SBCSFieldsReg_sbbusy & ~SBCSFieldsReg_sbbusyerror & ~_GEN_2)
SBDATAFieldsReg_1_1 <= SBDATAWrData_1[15:8];
else if (_sb2tlOpt_io_rdLoad_5)
SBDATAFieldsReg_1_1 <= _sb2tlOpt_io_dataOut;
if (SBDATAWrEn_1 & ~SBCSFieldsReg_sbbusy & ~SBCSFieldsReg_sbbusyerror & ~_GEN_2)
SBDATAFieldsReg_1_2 <= SBDATAWrData_1[23:16];
else if (_sb2tlOpt_io_rdLoad_6)
SBDATAFieldsReg_1_2 <= _sb2tlOpt_io_dataOut;
if (SBDATAWrEn_1 & ~SBCSFieldsReg_sbbusy & ~SBCSFieldsReg_sbbusyerror & ~_GEN_2)
SBDATAFieldsReg_1_3 <= SBDATAWrData_1[31:24];
else if (_sb2tlOpt_io_rdLoad_7)
SBDATAFieldsReg_1_3 <= _sb2tlOpt_io_dataOut;
if (_GEN) begin
if (_GEN_9)
ctrlStateReg <= {~_GEN_10, 1'h0};
else if (_GEN_12 & (hartExceptionWrEn | ~goReg & hartHaltedWrEn))
ctrlStateReg <= 2'h0;
end
else if (_GEN_8)
ctrlStateReg <= 2'h1;
end
else begin
ABSTRACTAUTOReg_autoexecprogbuf <= 16'h0;
ABSTRACTAUTOReg_autoexecdata <= 12'h0;
COMMANDReg_cmdtype <= 8'h0;
COMMANDReg_control <= 24'h0;
abstractDataMem_0 <= 8'h0;
abstractDataMem_1 <= 8'h0;
abstractDataMem_2 <= 8'h0;
abstractDataMem_3 <= 8'h0;
abstractDataMem_4 <= 8'h0;
abstractDataMem_5 <= 8'h0;
abstractDataMem_6 <= 8'h0;
abstractDataMem_7 <= 8'h0;
programBufferMem_0 <= 8'h0;
programBufferMem_1 <= 8'h0;
programBufferMem_2 <= 8'h0;
programBufferMem_3 <= 8'h0;
programBufferMem_4 <= 8'h0;
programBufferMem_5 <= 8'h0;
programBufferMem_6 <= 8'h0;
programBufferMem_7 <= 8'h0;
programBufferMem_8 <= 8'h0;
programBufferMem_9 <= 8'h0;
programBufferMem_10 <= 8'h0;
programBufferMem_11 <= 8'h0;
programBufferMem_12 <= 8'h0;
programBufferMem_13 <= 8'h0;
programBufferMem_14 <= 8'h0;
programBufferMem_15 <= 8'h0;
programBufferMem_16 <= 8'h0;
programBufferMem_17 <= 8'h0;
programBufferMem_18 <= 8'h0;
programBufferMem_19 <= 8'h0;
programBufferMem_20 <= 8'h0;
programBufferMem_21 <= 8'h0;
programBufferMem_22 <= 8'h0;
programBufferMem_23 <= 8'h0;
programBufferMem_24 <= 8'h0;
programBufferMem_25 <= 8'h0;
programBufferMem_26 <= 8'h0;
programBufferMem_27 <= 8'h0;
programBufferMem_28 <= 8'h0;
programBufferMem_29 <= 8'h0;
programBufferMem_30 <= 8'h0;
programBufferMem_31 <= 8'h0;
programBufferMem_32 <= 8'h0;
programBufferMem_33 <= 8'h0;
programBufferMem_34 <= 8'h0;
programBufferMem_35 <= 8'h0;
programBufferMem_36 <= 8'h0;
programBufferMem_37 <= 8'h0;
programBufferMem_38 <= 8'h0;
programBufferMem_39 <= 8'h0;
programBufferMem_40 <= 8'h0;
programBufferMem_41 <= 8'h0;
programBufferMem_42 <= 8'h0;
programBufferMem_43 <= 8'h0;
programBufferMem_44 <= 8'h0;
programBufferMem_45 <= 8'h0;
programBufferMem_46 <= 8'h0;
programBufferMem_47 <= 8'h0;
programBufferMem_48 <= 8'h0;
programBufferMem_49 <= 8'h0;
programBufferMem_50 <= 8'h0;
programBufferMem_51 <= 8'h0;
programBufferMem_52 <= 8'h0;
programBufferMem_53 <= 8'h0;
programBufferMem_54 <= 8'h0;
programBufferMem_55 <= 8'h0;
programBufferMem_56 <= 8'h0;
programBufferMem_57 <= 8'h0;
programBufferMem_58 <= 8'h0;
programBufferMem_59 <= 8'h0;
programBufferMem_60 <= 8'h0;
programBufferMem_61 <= 8'h0;
programBufferMem_62 <= 8'h0;
programBufferMem_63 <= 8'h0;
SBCSFieldsReg_sbbusy <= sbBusy;
SBCSFieldsReg_sbaccess <= 3'h2;
SBADDRESSFieldsReg_0 <= 32'h0;
SBDATAFieldsReg_0_0 <= 8'h0;
SBDATAFieldsReg_0_1 <= 8'h0;
SBDATAFieldsReg_0_2 <= 8'h0;
SBDATAFieldsReg_0_3 <= 8'h0;
SBDATAFieldsReg_1_0 <= 8'h0;
SBDATAFieldsReg_1_1 <= 8'h0;
SBDATAFieldsReg_1_2 <= 8'h0;
SBDATAFieldsReg_1_3 <= 8'h0;
ctrlStateReg <= 2'h0;
end
SBCSFieldsReg_sbbusyerror <=
~(~io_dmactive | out_woready_9 & auto_dmi_in_a_bits_mask[2]
& auto_dmi_in_a_bits_data[22])
& (anyAddressWrEn & sbBusy
| (SBDATARdEn_0 | _out_rofireMux_T_1 & out_backSel_61
& ~(auto_dmi_in_a_bits_address[8]) & (|out_backMask) | SBDATAWrEn_0
| SBDATAWrEn_1) & sbBusy | SBCSFieldsReg_sbbusyerror);
SBCSFieldsReg_sbreadonaddr <=
io_dmactive
& (out_woready_9 & auto_dmi_in_a_bits_mask[2]
? auto_dmi_in_a_bits_data[20]
: SBCSFieldsReg_sbreadonaddr);
SBCSFieldsReg_sbautoincrement <=
io_dmactive
& (out_woready_9 & auto_dmi_in_a_bits_mask[2]
? auto_dmi_in_a_bits_data[16]
: SBCSFieldsReg_sbautoincrement);
SBCSFieldsReg_sbreadondata <=
io_dmactive
& (out_woready_9 & auto_dmi_in_a_bits_mask[1]
? auto_dmi_in_a_bits_data[15]
: SBCSFieldsReg_sbreadondata);
sbErrorReg_0 <=
~(~io_dmactive | sberrorWrEn & auto_dmi_in_a_bits_data[12] | sb2tlOpt_io_wrEn
& ~_sb2tlOpt_io_wrLegal | sb2tlOpt_io_rdEn & ~_sb2tlOpt_io_rdLegal)
& (_sbErrorReg_2_T_10 & sbAlignmentError | ~(_sbErrorReg_2_T_10 & sbAccessError)
& (_sbErrorReg_2_T_12 & _sb2tlOpt_io_respError | sbErrorReg_0));
sbErrorReg_1 <=
~(~io_dmactive | sberrorWrEn & auto_dmi_in_a_bits_data[13])
& (sb2tlOpt_io_wrEn & ~_sb2tlOpt_io_wrLegal | sb2tlOpt_io_rdEn
& ~_sb2tlOpt_io_rdLegal | _sbErrorReg_2_T_10 & sbAlignmentError
| ~(_sbErrorReg_2_T_10 & sbAccessError)
& (_sbErrorReg_2_T_12 & _sb2tlOpt_io_respError | sbErrorReg_1));
sbErrorReg_2 <=
~(~io_dmactive | sberrorWrEn & auto_dmi_in_a_bits_data[14] | sb2tlOpt_io_wrEn
& ~_sb2tlOpt_io_wrLegal | sb2tlOpt_io_rdEn & ~_sb2tlOpt_io_rdLegal
| _sbErrorReg_2_T_10 & sbAlignmentError)
& (_sbErrorReg_2_T_10 & sbAccessError | _sbErrorReg_2_T_12 & _sb2tlOpt_io_respError
| sbErrorReg_2);
goReg <= io_dmactive & (goAbstract | ~hartGoingWrEn & goReg);
if (goAbstract) begin
abstractGeneratedMem_0 <=
COMMANDReg_control[17]
? (COMMANDReg_control[16]
? {17'h7000, COMMANDReg_control[22:20], COMMANDReg_control[4:0], 7'h3}
: {7'h1C,
COMMANDReg_control[4:0],
5'h0,
COMMANDReg_control[22:20],
12'h23})
: 32'h13;
abstractGeneratedMem_1 <= COMMANDReg_control[18] ? 32'h13 : 32'h100073;
end
if (reset)
hrmaskReg_0 <= 1'h0;
else
hrmaskReg_0 <=
io_dmactive & (io_innerCtrl_valid ? io_innerCtrl_bits_hrmask_0 : hrmaskReg_0);
end // always @(posedge)
always @(posedge clock or posedge reset) begin
if (reset)
hrDebugIntReg_0 <= 1'h0;
else
hrDebugIntReg_0 <=
io_dmactive & hrmaskReg_0
& (_hartIsInResetSync_0_debug_hartReset_0_io_q | hrDebugIntReg_0
& ~haltedBitRegs);
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
initial begin
if (reset)
hrDebugIntReg_0 = 1'h0;
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
SBToTL sb2tlOpt (
.clock (io_tl_clock),
.reset (io_tl_reset),
.auto_out_a_ready (auto_sb2tlOpt_out_a_ready),
.auto_out_a_valid (auto_sb2tlOpt_out_a_valid),
.auto_out_a_bits_opcode (auto_sb2tlOpt_out_a_bits_opcode),
.auto_out_a_bits_size (auto_sb2tlOpt_out_a_bits_size),
.auto_out_a_bits_address (auto_sb2tlOpt_out_a_bits_address),
.auto_out_a_bits_data (auto_sb2tlOpt_out_a_bits_data),
.auto_out_d_ready (auto_sb2tlOpt_out_d_ready),
.auto_out_d_valid (auto_sb2tlOpt_out_d_valid),
.auto_out_d_bits_opcode (auto_sb2tlOpt_out_d_bits_opcode),
.auto_out_d_bits_param (auto_sb2tlOpt_out_d_bits_param),
.auto_out_d_bits_size (auto_sb2tlOpt_out_d_bits_size),
.auto_out_d_bits_sink (auto_sb2tlOpt_out_d_bits_sink),
.auto_out_d_bits_denied (auto_sb2tlOpt_out_d_bits_denied),
.auto_out_d_bits_data (auto_sb2tlOpt_out_d_bits_data),
.auto_out_d_bits_corrupt (auto_sb2tlOpt_out_d_bits_corrupt),
.io_rdEn (sb2tlOpt_io_rdEn),
.io_wrEn (sb2tlOpt_io_wrEn),
.io_addrIn
({96'h0, anyAddressWrEn ? auto_dmi_in_a_bits_data : SBADDRESSFieldsReg_0}),
.io_dataIn
({64'h0,
sb2tlOpt_io_wrEn
? {SBDATAWrData_1, SBDATAWrData_0}
: {SBDATAFieldsReg_1_3,
SBDATAFieldsReg_1_2,
SBDATAFieldsReg_1_1,
SBDATAFieldsReg_1_0,
SBDATAFieldsReg_0_3,
SBDATAFieldsReg_0_2,
SBDATAFieldsReg_0_1,
SBDATAFieldsReg_0_0}}),
.io_sizeIn (SBCSFieldsReg_sbaccess),
.io_rdLegal (_sb2tlOpt_io_rdLegal),
.io_wrLegal (_sb2tlOpt_io_wrLegal),
.io_rdDone (_sb2tlOpt_io_rdDone),
.io_wrDone (_sb2tlOpt_io_wrDone),
.io_respError (_sb2tlOpt_io_respError),
.io_dataOut (_sb2tlOpt_io_dataOut),
.io_rdLoad_0 (_sb2tlOpt_io_rdLoad_0),
.io_rdLoad_1 (_sb2tlOpt_io_rdLoad_1),
.io_rdLoad_2 (_sb2tlOpt_io_rdLoad_2),
.io_rdLoad_3 (_sb2tlOpt_io_rdLoad_3),
.io_rdLoad_4 (_sb2tlOpt_io_rdLoad_4),
.io_rdLoad_5 (_sb2tlOpt_io_rdLoad_5),
.io_rdLoad_6 (_sb2tlOpt_io_rdLoad_6),
.io_rdLoad_7 (_sb2tlOpt_io_rdLoad_7),
.io_sbStateOut (_sb2tlOpt_io_sbStateOut)
);
AsyncResetSynchronizerShiftReg_w1_d3_i0 hartIsInResetSync_0_debug_hartReset_0 (
.clock (clock),
.reset (reset),
.io_d (io_hartIsInReset_0),
.io_q (_hartIsInResetSync_0_debug_hartReset_0_io_q)
);
assign auto_tl_in_a_ready = auto_tl_in_d_ready;
assign auto_tl_in_d_valid = auto_tl_in_a_valid;
assign auto_tl_in_d_bits_opcode = {2'h0, auto_tl_in_a_bits_opcode == 3'h4};
assign auto_tl_in_d_bits_size = auto_tl_in_a_bits_size;
assign auto_tl_in_d_bits_source = auto_tl_in_a_bits_source;
assign auto_tl_in_d_bits_data =
_GEN_5[auto_tl_in_a_bits_address[10:3]]
? _GEN_6[auto_tl_in_a_bits_address[10:3]]
: 64'h0;
assign auto_dmi_in_a_ready = auto_dmi_in_d_ready;
assign auto_dmi_in_d_valid = auto_dmi_in_a_valid;
assign auto_dmi_in_d_bits_opcode = {2'h0, in_bits_read};
assign auto_dmi_in_d_bits_size = auto_dmi_in_a_bits_size;
assign auto_dmi_in_d_bits_source = auto_dmi_in_a_bits_source;
assign auto_dmi_in_d_bits_data =
(_out_out_bits_data_T_28
? auto_dmi_in_a_bits_address[8]
: ~(auto_dmi_in_a_bits_address[7:2] == 6'h4
| auto_dmi_in_a_bits_address[7:2] == 6'h5
| auto_dmi_in_a_bits_address[7:2] == 6'h11
| auto_dmi_in_a_bits_address[7:2] == 6'h13
| auto_dmi_in_a_bits_address[7:2] == 6'h16
| auto_dmi_in_a_bits_address[7:2] == 6'h17
| auto_dmi_in_a_bits_address[7:2] == 6'h18
| auto_dmi_in_a_bits_address[7:2] == 6'h20
| auto_dmi_in_a_bits_address[7:2] == 6'h21
| auto_dmi_in_a_bits_address[7:2] == 6'h22
| auto_dmi_in_a_bits_address[7:2] == 6'h23
| auto_dmi_in_a_bits_address[7:2] == 6'h24
| auto_dmi_in_a_bits_address[7:2] == 6'h25
| auto_dmi_in_a_bits_address[7:2] == 6'h26
| auto_dmi_in_a_bits_address[7:2] == 6'h27
| auto_dmi_in_a_bits_address[7:2] == 6'h28
| auto_dmi_in_a_bits_address[7:2] == 6'h29
| auto_dmi_in_a_bits_address[7:2] == 6'h2A
| auto_dmi_in_a_bits_address[7:2] == 6'h2B
| auto_dmi_in_a_bits_address[7:2] == 6'h2C
| auto_dmi_in_a_bits_address[7:2] == 6'h2D
| auto_dmi_in_a_bits_address[7:2] == 6'h2E
| auto_dmi_in_a_bits_address[7:2] == 6'h2F
| auto_dmi_in_a_bits_address[7:2] == 6'h38
| auto_dmi_in_a_bits_address[7:2] == 6'h39
| auto_dmi_in_a_bits_address[7:2] == 6'h3C
| auto_dmi_in_a_bits_address[7:2] == 6'h3D) | ~(auto_dmi_in_a_bits_address[8]))
? (_out_out_bits_data_T_28
? _GEN_1
: auto_dmi_in_a_bits_address[7:2] == 6'h4
? {abstractDataMem_3,
abstractDataMem_2,
abstractDataMem_1,
abstractDataMem_0}
: auto_dmi_in_a_bits_address[7:2] == 6'h5
? {abstractDataMem_7,
abstractDataMem_6,
abstractDataMem_5,
abstractDataMem_4}
: auto_dmi_in_a_bits_address[7:2] == 6'h11
? {12'h0,
{2{haveResetBitRegs}},
{2{resumereq ? ~resumeReqRegs & _GEN_0 : ~resumeReqRegs}},
4'h0,
~haltedBitRegs,
~haltedBitRegs,
{2{haltedBitRegs}},
8'hA2}
: auto_dmi_in_a_bits_address[7:2] == 6'h13
? _GEN_1
: auto_dmi_in_a_bits_address[7:2] == 6'h16
? {19'h8000,
abstractCommandBusy,
1'h0,
ABSTRACTCSReg_cmderr,
8'h2}
: auto_dmi_in_a_bits_address[7:2] == 6'h17
? {COMMANDReg_cmdtype, COMMANDReg_control}
: auto_dmi_in_a_bits_address[7:2] == 6'h18
? {ABSTRACTAUTOReg_autoexecprogbuf,
14'h0,
ABSTRACTAUTOReg_autoexecdata[1:0]}
: auto_dmi_in_a_bits_address[7:2] == 6'h20
? {programBufferMem_3,
programBufferMem_2,
programBufferMem_1,
programBufferMem_0}
: auto_dmi_in_a_bits_address[7:2] == 6'h21
? {programBufferMem_7,
programBufferMem_6,
programBufferMem_5,
programBufferMem_4}
: auto_dmi_in_a_bits_address[7:2] == 6'h22
? {programBufferMem_11,
programBufferMem_10,
programBufferMem_9,
programBufferMem_8}
: auto_dmi_in_a_bits_address[7:2] == 6'h23
? {programBufferMem_15,
programBufferMem_14,
programBufferMem_13,
programBufferMem_12}
: auto_dmi_in_a_bits_address[7:2] == 6'h24
? {programBufferMem_19,
programBufferMem_18,
programBufferMem_17,
programBufferMem_16}
: auto_dmi_in_a_bits_address[7:2] == 6'h25
? {programBufferMem_23,
programBufferMem_22,
programBufferMem_21,
programBufferMem_20}
: auto_dmi_in_a_bits_address[7:2] == 6'h26
? {programBufferMem_27,
programBufferMem_26,
programBufferMem_25,
programBufferMem_24}
: auto_dmi_in_a_bits_address[7:2] == 6'h27
? {programBufferMem_31,
programBufferMem_30,
programBufferMem_29,
programBufferMem_28}
: auto_dmi_in_a_bits_address[7:2] == 6'h28
? {programBufferMem_35,
programBufferMem_34,
programBufferMem_33,
programBufferMem_32}
: auto_dmi_in_a_bits_address[7:2] == 6'h29
? {programBufferMem_39,
programBufferMem_38,
programBufferMem_37,
programBufferMem_36}
: auto_dmi_in_a_bits_address[7:2] == 6'h2A
? {programBufferMem_43,
programBufferMem_42,
programBufferMem_41,
programBufferMem_40}
: auto_dmi_in_a_bits_address[7:2] == 6'h2B
? {programBufferMem_47,
programBufferMem_46,
programBufferMem_45,
programBufferMem_44}
: auto_dmi_in_a_bits_address[7:2] == 6'h2C
? {programBufferMem_51,
programBufferMem_50,
programBufferMem_49,
programBufferMem_48}
: auto_dmi_in_a_bits_address[7:2] == 6'h2D
? {programBufferMem_55,
programBufferMem_54,
programBufferMem_53,
programBufferMem_52}
: auto_dmi_in_a_bits_address[7:2] == 6'h2E
? {programBufferMem_59,
programBufferMem_58,
programBufferMem_57,
programBufferMem_56}
: auto_dmi_in_a_bits_address[7:2] == 6'h2F
? {programBufferMem_63,
programBufferMem_62,
programBufferMem_61,
programBufferMem_60}
: auto_dmi_in_a_bits_address[7:2] == 6'h38
? {9'h40,
SBCSFieldsReg_sbbusyerror,
sbBusy,
SBCSFieldsReg_sbreadonaddr,
SBCSFieldsReg_sbaccess,
SBCSFieldsReg_sbautoincrement,
SBCSFieldsReg_sbreadondata,
sbErrorReg_2,
sbErrorReg_1,
sbErrorReg_0,
12'h40F}
: auto_dmi_in_a_bits_address[7:2] == 6'h39
? SBADDRESSFieldsReg_0
: auto_dmi_in_a_bits_address[7:2] == 6'h3C
? {SBDATAFieldsReg_0_3,
SBDATAFieldsReg_0_2,
SBDATAFieldsReg_0_1,
SBDATAFieldsReg_0_0}
: auto_dmi_in_a_bits_address[7:2] == 6'h3D
? {SBDATAFieldsReg_1_3,
SBDATAFieldsReg_1_2,
SBDATAFieldsReg_1_1,
SBDATAFieldsReg_1_0}
: 32'h0)
: 32'h0;
assign io_hgDebugInt_0 = hrDebugIntReg_0;
endmodule
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