onur
22 lines
479 B
Systemverilog
22 lines
479 B
Systemverilog
// Generated by CIRCT firtool-1.151.0
|
|
// VCS coverage exclude_file
|
|
module ram_2x77(
|
|
input R0_addr,
|
|
R0_en,
|
|
R0_clk,
|
|
output [76:0] R0_data,
|
|
input W0_addr,
|
|
W0_en,
|
|
W0_clk,
|
|
input [76:0] W0_data
|
|
);
|
|
|
|
reg [76:0] Memory[0:1];
|
|
always @(posedge W0_clk) begin
|
|
if (W0_en)
|
|
Memory[W0_addr] <= W0_data;
|
|
end // always @(posedge)
|
|
assign R0_data = R0_en ? Memory[R0_addr] : 77'bx;
|
|
endmodule
|
|
|