onur
105 lines
3.1 KiB
Systemverilog
105 lines
3.1 KiB
Systemverilog
`timescale 1ns/1ps
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module max2771_spi_engine #(
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parameter integer CLOCK_HZ = 50_000_000,
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parameter integer MAX_SCLK_HZ = 4_000_000
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) (
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input wire clk,
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input wire rst_n,
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input wire start,
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input wire read_not_write,
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input wire [3:0] address,
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input wire [31:0] write_data,
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output reg [31:0] read_data,
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output reg busy,
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output wire ready,
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output reg sclk,
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output reg csn,
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input wire sdata_i,
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output reg sdata_o,
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output reg sdata_oe
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);
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// Ceiling division keeps SCLK at or below the MAX2771 4 MHz limit.
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localparam integer HALF_PERIOD_CYCLES =
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(CLOCK_HZ + (2 * MAX_SCLK_HZ) - 1) / (2 * MAX_SCLK_HZ);
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localparam integer CS_INACTIVE_CYCLES =
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(CLOCK_HZ + 10_000_000 - 1) / 10_000_000;
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reg [47:0] tx_shift;
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reg [31:0] rx_shift;
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reg [5:0] bit_index;
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integer half_count;
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integer inactive_count;
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reg transaction_is_read;
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assign ready = !busy && (inactive_count == 0);
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initial begin
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if (CLOCK_HZ <= 0)
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$error("CLOCK_HZ must be positive");
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if (MAX_SCLK_HZ <= 0)
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$error("MAX_SCLK_HZ must be positive");
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if (HALF_PERIOD_CYCLES < 1)
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$error("HALF_PERIOD_CYCLES must be at least one");
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end
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always @(posedge clk) begin
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if (!rst_n) begin
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read_data <= 32'd0;
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busy <= 1'b0;
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sclk <= 1'b0;
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csn <= 1'b1;
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sdata_o <= 1'b0;
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sdata_oe <= 1'b0;
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tx_shift <= 48'd0;
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rx_shift <= 32'd0;
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bit_index <= 6'd0;
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half_count <= 0;
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inactive_count <= 0;
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transaction_is_read <= 1'b0;
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end else if (busy) begin
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if (half_count != 0) begin
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half_count <= half_count - 1;
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end else begin
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half_count <= HALF_PERIOD_CYCLES - 1;
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if (!sclk) begin
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// MAX2771 samples input and the host samples read data on rising SCLK.
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sclk <= 1'b1;
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if (transaction_is_read && (bit_index >= 6'd16))
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rx_shift <= {rx_shift[30:0], sdata_i};
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end else begin
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// Both sides change or release SDATA on falling SCLK.
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sclk <= 1'b0;
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if (bit_index == 6'd47) begin
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read_data <= rx_shift;
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busy <= 1'b0;
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csn <= 1'b1;
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sdata_oe <= 1'b0;
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inactive_count <= CS_INACTIVE_CYCLES;
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end else begin
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bit_index <= bit_index + 1'b1;
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tx_shift <= {tx_shift[46:0], 1'b0};
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sdata_o <= tx_shift[46];
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if (transaction_is_read && (bit_index == 6'd12))
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sdata_oe <= 1'b0;
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end
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end
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end
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end else if (inactive_count != 0) begin
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inactive_count <= inactive_count - 1;
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end else if (start) begin
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// Frame: A[11:0], R/W, three turnaround bits, D[31:0]. A[11:4] are zero.
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tx_shift <= {8'd0, address, read_not_write, 3'd0, write_data};
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rx_shift <= 32'd0;
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bit_index <= 6'd0;
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transaction_is_read <= read_not_write;
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busy <= 1'b1;
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csn <= 1'b0;
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sclk <= 1'b0;
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sdata_o <= 1'b0;
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sdata_oe <= 1'b1;
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half_count <= HALF_PERIOD_CYCLES - 1;
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end
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end
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endmodule
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