onur
1.6 KiB
MAX2771 SPI Register Test
This bare-metal application exercises the dedicated MAX2771 three-wire SPI IP
at 0x10016000. It does not use or alter the generic PMOD SPI peripheral.
The test uses the complete default register table from the
MAX2771 data sheet.
It writes registers 0x0 through 0xA, reads each register back immediately,
then performs a second full read sweep and prints all values. Registers 0x0
and 0x9 therefore receive the mandatory reserved-bit values required after
every MAX2771 power cycle.
Build directly:
make -C soc/software max2771-spi-test
Build through a board flow:
make -C targets/fpga/genesys2 software APP=max2771_spi_test
make -C targets/fpga/vcu118 software APP=max2771_spi_test
For a fast RAM-loaded Genesys 2 test:
make -C targets/fpga/genesys2 debug-load APP=max2771_spi_test
make -C targets/fpga/genesys2 uart-listen
Expected final output is:
PASS,MAX2771 defaults programmed and verified
EV Kit Connection
The EV kit already has a MAX32625 PICO MCU connected to SPI_CLK, SPI_CSN,
and SPI_DATA. Before connecting the FPGA, disconnect that controller or put
all three MCU pins in high impedance and do not run the EV kit GUI. Two active
masters on SPI_DATA can cause electrical contention.
Connect SCLK, CSN, the single bidirectional SDATA, and a common ground.
Power the EV kit according to its own guide. Do not connect the FPGA board's
PMOD power pin to an independently powered EV kit.