82 lines
2.3 KiB
C
82 lines
2.3 KiB
C
#include <stdint.h>
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#include <stdio.h>
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#include "bsp/max2771_spi.h"
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#include "bsp/soc.h"
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#include "bsp/uart.h"
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/* MAX2771 data sheet Table 2, including the mandatory reserved-bit values. */
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static const uint32_t max2771_default_registers[BSP_MAX2771_REGISTER_COUNT] = {
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0xbea41603u,
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0x20550288u,
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0x0eafa1dcu,
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0x698c0008u,
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0x00c00080u,
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0x08000070u,
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0x08000000u,
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0x010061b2u,
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0x01e0f401u,
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0x00c00002u,
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0x010061b0u
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};
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static int report_error(const char *operation,
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unsigned int address,
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bsp_max2771_status_t status)
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{
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printf("FAIL,%s,reg=0x%x,status=%d\n", operation, address, (int)status);
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bsp_uart_wait_tx_idle();
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return 1;
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}
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int main(void)
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{
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printf("\nMAX2771 dedicated three-wire SPI test\n");
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printf("MMIO,0x%08lx\n", (unsigned long)BSP_MAX2771_SPI_BASE);
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bsp_max2771_status_t status = bsp_max2771_spi_init();
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if (status != BSP_MAX2771_OK) {
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return report_error("init", 0u, status);
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}
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printf("CLOCK,input_hz=%lu,expected_input_hz=%lu,sclk_hz=%lu,half_cycles=%lu,max_hz=%u\n",
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(unsigned long)bsp_max2771_input_clock_hz(),
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(unsigned long)BSP_MAX2771_INPUT_CLOCK_HZ,
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(unsigned long)bsp_max2771_sclk_hz(),
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(unsigned long)bsp_max2771_half_period_cycles(),
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BSP_MAX2771_MAX_SCLK_HZ);
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for (unsigned int address = 0u;
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address < BSP_MAX2771_REGISTER_COUNT;
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++address) {
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status = bsp_max2771_write_verified(
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(uint8_t)address, max2771_default_registers[address]);
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if (status != BSP_MAX2771_OK) {
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return report_error("write_verify", address, status);
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}
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}
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for (unsigned int address = 0u;
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address < BSP_MAX2771_REGISTER_COUNT;
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++address) {
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uint32_t value = 0u;
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status = bsp_max2771_read((uint8_t)address, &value);
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if (status != BSP_MAX2771_OK) {
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return report_error("read", address, status);
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}
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printf("REGISTER,0x%x,0x%08lx\n", address, (unsigned long)value);
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if (value != max2771_default_registers[address]) {
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printf("FAIL,read_verify,reg=0x%x,expected=0x%08lx,actual=0x%08lx\n",
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address,
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(unsigned long)max2771_default_registers[address],
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(unsigned long)value);
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bsp_uart_wait_tx_idle();
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return 1;
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}
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}
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printf("PASS,MAX2771 defaults programmed and verified\n");
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bsp_uart_wait_tx_idle();
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return 0;
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}
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