337 lines
11 KiB
Markdown
337 lines
11 KiB
Markdown
# Rocket Project
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Bu agac VCU118/Genesys2 FPGA ve ASIC-style Rocket akislari icin sade proje duzenidir.
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Upstream Rocket-Chip kaynaklari daginik kok klasorlerde tutulmaz; gerekli
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upstream kaynaklar `hardware/upstream/rocket-chip/` altindadir.
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## Kisa Harita
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```text
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hardware/
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soc/scala/ Proje Scala/Chisel SoC katmani
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generated/ FIRRTL ve SystemVerilog dump alani
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fpga/vcu118/rtl/ VCU118 ek RTL
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fpga/vcu118/constraints/ VCU118 XDC
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fpga/genesys2/rtl/ Genesys2 ek RTL
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fpga/genesys2/constraints/ Genesys2 XDC
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sim/fpga/vcu118/ FPGA smoke/sim girisi
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sim/asic/rocket/ ASIC testbench, modeller, wave.do
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external/gps/rtl/ GPS RTL kaynaklari ve filelist
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upstream/rocket-chip/ Gerekli upstream Rocket-Chip src ve bootrom
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soc/software/ Bootloader, BSP, uygulamalar, flash image tool
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targets/fpga/vcu118/ VCU118 build/programlama akisi
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targets/fpga/genesys2/ Genesys2 build/programlama akisi
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targets/asic/rocket/ ASIC wrapper/filelist/sim akisi
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setup_tools.sh /tools/soc-tools host araci kurulum betigi
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```
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## Gelistirme Araclari
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Mill, JDK, CIRCT/firtool ve Z3 makineye/işletim sistemine ozel binary
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paketlerdir; Git'e eklenmezler. Linux x86-64 host araclarini sabit surum ve
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SHA256 kontrolleriyle `/tools/soc-tools` altina kurmak icin:
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```sh
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./setup_tools.sh
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```
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Proje araclarini ve RISC-V bare-metal toolchain'i shell'e eklemek icin:
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```sh
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source source.sh
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make doctor
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```
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`source.sh`, RISC-V GCC'yi sirasiyla `RISCV_TOOLCHAIN`, `TOOLCHAIN`, proje-ici
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`tools/local/riscv/bin`, `/tools/toolchain/bin`, `/tools/toolchains/bin` ve
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`PATH` icinde arar. Standart olmayan bir kurulum icin:
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```sh
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RISCV_TOOLCHAIN=/opt/riscv source source.sh
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```
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Ayni ayar shell'i degistirmeden Make'e de verilebilir:
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```sh
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make fpga-rtl RISCV_TOOLCHAIN=/opt/riscv
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```
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`setup_tools.sh` host tarafindaki Scala/Chisel uretim araclarini kurar. RISC-V
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bare-metal toolchain buyuk ve ayri bir urun oldugu icin indirilmez; `source.sh`
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tarafindan mevcut `/tools/toolchains` kurulumundan veya `RISCV_TOOLCHAIN`
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degiskeninden bulunur.
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## Ana Komutlar
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```sh
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make help
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make fpga-rtl
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make fpga-bitstream
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make fpga-elf-flash-image
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make fpga-mcs
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make fpga-program
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make fpga-flash
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make fpga-flash-bitstream
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make fpga-flash-mcs
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make fpga-flash-all
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make asic-rtl
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make asic-sim
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```
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GPS bare-metal uygulamasini derlemek ve FPGA uzerinde GDB ile RAM'e yuklemek:
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```sh
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make -C soc/software app APP=gps_system
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make -C targets/fpga/vcu118 debug-load APP=gps_system
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```
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Alt girisler:
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```sh
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make -C hardware/soc help
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make -C hardware/fpga/vcu118/rtl help
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make -C hardware/sim/fpga/vcu118 help
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make -C targets/fpga/vcu118 help
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make -C targets/fpga/genesys2 help
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make -C targets/asic/rocket help
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```
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## FPGA Kart Secimi ve RF Girisi
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FPGA karti kok Makefile'dan `FPGA_BOARD` ile secilir:
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```sh
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make FPGA_BOARD=vcu118 fpga-config
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make FPGA_BOARD=genesys2 fpga-config
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```
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Top-level `BOARD=...` alias'i da desteklenir. Orneklerde Genesys2 kullanilir:
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```sh
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make BOARD=genesys2 fpga-config
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```
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Top-level hedeflerde tireli isimler tercih edilir (`fpga-program` gibi).
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Yanlislikla underscore kullanilmasi durumunda yaygin FPGA hedefleri icin
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alias'lar da vardir (`fpga_program`, `fpga_debug_openocd` gibi).
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`fpga-config` secilen kartin clock, flash, UART, DTIM ve RF ayarlarini
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gosterir. RF kaynagi `RF_INPUT_MODE` ile secilir:
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```text
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RF_INPUT_MODE=pmod Varsayilan. Harici 4-bit RF data + RF clock PMOD'dan gelir.
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RF_INPUT_MODE=generated Dahili RF clock uretilir, RF data sifira baglanir.
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RF_INPUT_MODE=ethernet Kart bazli raw-Ethernet RF streamer path'i.
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```
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Top-level FPGA wrapper'lar elle yazilmaz; `targets/fpga/*/tools/gen_*_wrapper.py`
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scriptleri tarafindan uretilir. Bu yuzden RF secimi RTL `ifdef` ile degil,
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generator parametresi ile yapilir. `make rtl` ve Vivado `build.tcl` ayni
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`RF_INPUT_MODE` degerini wrapper generator'a gecirir.
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Varsayilan `pmod` modunda Ethernet RF IP/RTL okunmaz ve top'ta Ethernet PHY
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portlari olusmaz. Ethernet RF akisi gerektiginde:
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```sh
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make -C targets/fpga/vcu118 bitstream RF_INPUT_MODE=ethernet
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sudo make -C targets/fpga/vcu118 eth-rf-send
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make -C targets/fpga/genesys2 bitstream RF_INPUT_MODE=ethernet
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sudo make -C targets/fpga/genesys2 eth-rf-send
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```
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PMOD RF pinleri ve voltajlari:
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```text
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Genesys2 JA, connector ve FPGA tarafi 3.3 V:
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port FPGA pin PMOD pin FPGA I/O PMOD header level
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rf_clk_pmod U27 JA[0] LVCMOS33 3.3 V
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rf_data_pmod[0] U28 JA[1] LVCMOS33 3.3 V
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rf_data_pmod[1] T26 JA[2] LVCMOS33 3.3 V
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rf_data_pmod[2] T27 JA[3] LVCMOS33 3.3 V
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rf_data_pmod[3] T22 JA[4] LVCMOS33 3.3 V
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VCU118 PMOD0/J52, connector tarafi 3.3 V, FPGA U1 tarafi U41 level shifter
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uzerinden 1.8 V bank/LVCMOS18:
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port FPGA pin PMOD pin FPGA I/O PMOD header level
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rf_clk_pmod AY14 PMOD0_0 J52.1 LVCMOS18 3.3 V
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rf_data_pmod[0] AY15 PMOD0_1 J52.3 LVCMOS18 3.3 V
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rf_data_pmod[1] AW15 PMOD0_2 J52.5 LVCMOS18 3.3 V
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rf_data_pmod[2] AV15 PMOD0_3 J52.7 LVCMOS18 3.3 V
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rf_data_pmod[3] AV16 PMOD0_4 J52.2 LVCMOS18 3.3 V
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```
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VCU118'de disaridan PMOD header'a 3.3 V seviye verilir. FPGA U1 package
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pinlerine dogrudan 3.3 V uygulanmaz; o tarafta XDC `LVCMOS18` kullanir.
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PMOD SPI portu her RF modunda aktiftir ve ayri MMIO register block olarak
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`0x10015000` adresindedir. Kart uzerindeki konfig flash SPI'si `0x10014000`
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adresinde kalir. Yazilim driver'i single/quad calisma modunu `ctrl.bit2`
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uzerinden secer; single modda `dq[0]` MOSI, `dq[1]` MISO olarak kullanilir ve
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`dq[2:3]` high-Z kalir. Quad modda `dq[3:0]` birlikte kullanilir.
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```text
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Genesys2 PMOD JC, connector ve FPGA tarafi 3.3 V:
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port FPGA pin PMOD pin FPGA I/O PMOD header level
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pmod_spi_csn AC26 JC1 LVCMOS33 3.3 V
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pmod_spi_dq[0] AJ27 JC2 MOSI LVCMOS33 3.3 V
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pmod_spi_dq[1] AH30 JC3 MISO LVCMOS33 3.3 V
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pmod_spi_sck AK29 JC4 SCK LVCMOS33 3.3 V
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pmod_spi_dq[2] AD26 JC7 LVCMOS33 3.3 V
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pmod_spi_dq[3] AG30 JC8 LVCMOS33 3.3 V
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VCU118 PMOD1/J53, connector tarafi 3.3 V, FPGA U1 tarafi U42 level shifter
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uzerinden 1.2 V bank/LVCMOS12:
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port FPGA pin PMOD pin FPGA I/O PMOD header level
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pmod_spi_csn N28 PMOD1_0 J53.1 LVCMOS12 3.3 V
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pmod_spi_dq[0] M30 PMOD1_1 J53.3 MOSI LVCMOS12 3.3 V
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pmod_spi_dq[1] N30 PMOD1_2 J53.5 MISO LVCMOS12 3.3 V
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pmod_spi_sck P30 PMOD1_3 J53.7 SCK LVCMOS12 3.3 V
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pmod_spi_dq[2] P29 PMOD1_4 J53.2 LVCMOS12 3.3 V
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pmod_spi_dq[3] L31 PMOD1_5 J53.4 LVCMOS12 3.3 V
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```
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Sensorden gelen external interrupt hatti SPI'dan bagimsizdir. `pmod_irq`
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top-level input'u olarak PMOD'a alinir ve PLIC'te `BSP_PMOD_IRQ` (`11`)
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ID'siyle gorunur.
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```text
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Genesys2:
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port FPGA pin PMOD pin FPGA I/O PMOD header level
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pmod_irq AK30 JC9 LVCMOS33 3.3 V
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VCU118:
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port FPGA pin PMOD pin FPGA I/O PMOD header level
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pmod_irq M31 PMOD1_6 J53.6 LVCMOS12 3.3 V
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```
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Bu pinler mod bazli companion XDC dosyalarinda tutulur:
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`hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc`,
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`hardware/fpga/vcu118/constraints/vcu118_pmod_rf.xdc`,
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`hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc`,
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`hardware/fpga/vcu118/constraints/vcu118_pmod_spi.xdc`,
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`hardware/fpga/genesys2/constraints/genesys2_pmod_irq.xdc`,
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`hardware/fpga/vcu118/constraints/vcu118_pmod_irq.xdc`,
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`hardware/fpga/genesys2/constraints/genesys2_ethernet.xdc` ve
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`hardware/fpga/vcu118/constraints/vcu118_ethernet.xdc`.
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## FPGA Flash ve MCS Akislari
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Bu hedefler kok Makefile'dan secilen karta yonlenir. Genesys2 icin
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`BOARD=genesys2`, VCU118 icin `BOARD=vcu118` kullanilir. `APP` verilmezse
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varsayilan uygulama `hello_uart` olur.
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Sadece ELF'i derleyip bootloader'in okuyacagi flash-format app imajina cevirmek:
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```sh
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make BOARD=genesys2 APP=hello_uart fpga-elf-flash-image
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```
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Bu akista ELF dogrudan MCS'e girmez. Once su dosya uretilir:
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```text
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soc/out/flash/hello_uart.flash.bin
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```
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Yeni bitstream ve yeni aplikasyon ile birlesik MCS/BIN olusturmak:
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```sh
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make BOARD=genesys2 APP=hello_uart fpga-bitstream fpga-mcs
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```
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Genesys2 ciktilari:
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```text
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targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
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targets/fpga/genesys2/out/flash/genesys2_rocket.mcs
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targets/fpga/genesys2/out/flash/genesys2_rocket.bin
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```
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Birlesik MCS'i olusturup kart flash'ina yazmak:
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```sh
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make BOARD=genesys2 APP=hello_uart fpga-flash-mcs
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```
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Yeni bitstream de uretilsin, sonra birlesik MCS flash'a yazilsin:
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```sh
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make BOARD=genesys2 APP=hello_uart fpga-bitstream fpga-flash-mcs
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```
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Sadece bitstream region'ini kart flash'ina yazmak:
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```sh
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make BOARD=genesys2 fpga-flash-bitstream
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```
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Yeni bitstream uretip sadece bitstream region'ini yazmak:
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```sh
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make BOARD=genesys2 fpga-bitstream fpga-flash-bitstream
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```
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ELF'i flash formatina cevirip sadece app region'ini kart flash'ina yazmak:
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```sh
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make BOARD=genesys2 APP=hello_uart fpga-flash-app
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```
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`fpga-flash`, `fpga-flash-app` icin alias'tir:
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```sh
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make BOARD=genesys2 APP=hello_uart fpga-flash
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```
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Degisen bitstream ve app region'larini ayri MCS'lerle programlamak:
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```sh
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make BOARD=genesys2 APP=hello_uart fpga-flash-all
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```
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Flash programlama bittikten sonra FPGA her zaman otomatik olarak flash'taki
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kullanici bitstream'inden yeniden baslamaz. Kartin kalici flash'tan boot
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etmesini test etmek icin power-cycle/reconfigure yapin; sadece RAM/SRAM'e
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hemen yuklemek icin `fpga-program` kullanin:
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```sh
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make BOARD=genesys2 fpga-program
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```
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OpenOCD baslarken `LIBUSB_ERROR_BUSY` gorulurse JTAG kablosunu Vivado
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`hw_server` tutuyordur. Hardware Manager'i kapatin veya bu prosesleri durdurun:
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```sh
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pkill -u "$USER" -x hw_server || true
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pkill -u "$USER" -x cs_server || true
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make BOARD=genesys2 fpga-debug-openocd
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```
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Genesys2 flash yerlesimi:
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```text
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bitstream offset: 0x00000000
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app offset: 0x01800000
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flash size: 32 MiB
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interface: SPIx4
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```
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## GPS Reset Davranisi
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OpenOCD/GDB `monitor reset` yolu Rocket debug module `ndmreset` sinyalini
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assert eder. FPGA top wrapper'lari bu sinyali SoC resetine katar; bu reset hem
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Rocket core'a hem APB peripheral tarafina gider.
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GPS APB entegrasyonu reseti tek tel olarak kullanmaz. `APBGpsBlock` icinde
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`ResetCatchAndSync` ile APB/PCLK, acquisition 80 MHz, tracking 125 MHz ve
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RF/AFE clock domainleri icin ayri active-low resetler uretilir. Assert async,
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deassert ilgili clock domaininde 3 kademe senkronizedir. APB register wrapper
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lari `PRESETN` ile resetlenir; `acq_top`, `trck_top` ve `afe_top` ise kendi
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clock domain resetleriyle resetlenir.
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Not: Senkron deassert icin ilgili clock calismalidir. PMOD/RF clock yoksa
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RF/AFE domain reseti release olmaz; bu reset acisindan beklenen davranistir.
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Detayli dosya haritasi icin `PROJECT_LAYOUT.md` ve `hardware/README.md`.
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