1.2 KiB
Genesys2 JB1 direct PLIC test
This standalone image tests only the asynchronous PMOD interrupt path:
JB1 (V29) -> wrapper 3FF synchronizer -> Rocket interrupt bus -> PLIC 11
The input is LVCMOS33 with a weak FPGA pull-down. The Rocket PLIC gateway is level-sensitive, so the ISR masks source 11 on its first assertion before it completes the claim. This makes a hand-driven HIGH test one-shot and prevents an interrupt storm.
Build:
make -C soc/software/pmod_irq_test clean all
After loading build/pmod_irq_test.elf, wait for PMOD_IRQ_READY. Start with
JB1 disconnected, then connect JB1 to a Genesys2 PMOD 3.3 V pin once. A working
path prints PMOD_IRQ_PASS. Remove the 3.3 V connection before resetting or
reloading the image.
Never apply 5 V to JB1 and never short a PMOD supply pin to ground.
For a voltage-source-independent loopback test, connect the FPGA-driven JC4
SPI clock output directly to the JB1 interrupt input. After
LOOPBACK_READY, send t over UART. The firmware emits 16 SPI transfers;
the first SCK HIGH must produce PMOD_IRQ_PASS. This loopback is confined to
the standalone diagnostic and does not add GPIO or alter the production PLIC
path.