31 lines
1.2 KiB
Markdown
31 lines
1.2 KiB
Markdown
# Genesys2 JB1 direct PLIC test
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This standalone image tests only the asynchronous PMOD interrupt path:
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`JB1 (V29) -> wrapper 3FF synchronizer -> Rocket interrupt bus -> PLIC 11`
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The input is LVCMOS33 with a weak FPGA pull-down. The Rocket PLIC gateway is
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level-sensitive, so the ISR masks source 11 on its first assertion before it
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completes the claim. This makes a hand-driven HIGH test one-shot and prevents
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an interrupt storm.
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Build:
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```sh
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make -C soc/software/pmod_irq_test clean all
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```
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After loading `build/pmod_irq_test.elf`, wait for `PMOD_IRQ_READY`. Start with
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JB1 disconnected, then connect JB1 to a Genesys2 PMOD 3.3 V pin once. A working
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path prints `PMOD_IRQ_PASS`. Remove the 3.3 V connection before resetting or
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reloading the image.
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Never apply 5 V to JB1 and never short a PMOD supply pin to ground.
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For a voltage-source-independent loopback test, connect the FPGA-driven JC4
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SPI clock output directly to the JB1 interrupt input. After
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`LOOPBACK_READY`, send `t` over UART. The firmware emits 16 SPI transfers;
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the first SCK HIGH must produce `PMOD_IRQ_PASS`. This loopback is confined to
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the standalone diagnostic and does not add GPIO or alter the production PLIC
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path.
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