95 lines
4.1 KiB
Markdown
95 lines
4.1 KiB
Markdown
# Rocket ASIC Flow
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This flow builds the same Rocket SoC for an ASIC-style shell: no FPGA clock,
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startup, BSCAN, or flash access primitives are instantiated. The top level uses
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plain clock/reset, UART, SPI, and JTAG pins.
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## Commands
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The ASIC flow is driven directly by this directory's `Makefile`; there is no
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separate flow dispatcher script.
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```sh
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make -C targets/asic/rocket rtl
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make -C targets/asic/rocket sim-rtl
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make -C targets/asic/rocket vlog-soc
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make -C targets/asic/rocket vlog-tb
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make -C targets/asic/rocket sim
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make -C targets/asic/rocket sim-pmod-irq
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make -C targets/asic/rocket sim-pmod-irq-rtl
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make -C targets/asic/rocket sim GUI=1
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```
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The default simulation app is `hello_uart`.
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The ASIC Makefile always checks the bootloader build configuration before
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hardware generation. This prevents a previously built Genesys2 image (50 MHz
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UART and a different flash offset) from being silently embedded in the ASIC
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BootROM; the ASIC defaults are 100 MHz, 115200 baud, and flash offset
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`0x06000000`.
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`sim-pmod-irq` drives the ASIC top-level `pmod_irq` input with four
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asynchronous square-wave periods, checks that TLPLIC source 10 becomes pending
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(architectural device ID 11), and boots the standalone `pmod_irq_test`
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firmware. PASS therefore requires both the RTL pending bit and a successful CPU
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PLIC interrupt/ISR return; a pin toggle alone is not accepted.
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`sim-pmod-irq-rtl` applies the same four asynchronous periods but finishes as
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soon as all four input rising edges and the PLIC device-11 pending state have
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been observed. It skips the slow bootloader/SPI-flash/firmware phase and is the
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fast regression for the ASIC input-to-PLIC hardware route. It does not claim to
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test the C interrupt handler; use `sim-pmod-irq` for that end-to-end check.
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## PMOD IRQ ASIC simulation result
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Verified on 2026-07-14 with QuestaSim 2021.2_1:
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```text
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ASIC PMOD IRQ: PLIC device 11 pending observed
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UART: Flash JEDEC ID: 0x0020bb21
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UART: Load: flash 0x06000040 -> mem 0x80000000, size 0x00000908
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UART: CRC ok, jumping 0x80000000
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C main returned 0
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ASIC PMOD IRQ PASS: rises=4 pending_seen=1
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ASIC sanity PASS
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Errors: 0
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```
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The fast RTL-only regression also passed at simulation time 1455 ns with four
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rising edges and PLIC device 11 pending. The full test completed at simulation
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time 50,972,035 ns. In `pmod_irq_test`, return code zero is emitted only after
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the expected device-11 ISR increments its interrupt counter.
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`make -C targets/asic/rocket sim GUI=1` opens the Questa/ModelSim graphical simulator,
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loads `asic_rocket_tb` with `-voptargs="+acc"`, sources
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`hardware/sim/asic/rocket/wave.do`, sets `onfinish stop`, and runs only `0 ns`
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so the GUI is ready for manual waveform/debug work.
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Generated outputs:
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- `soc/out/software/`: common bootloader and application ELF/img outputs.
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- `soc/out/flash/hello_uart.flash.hex`: SPI flash model contents loaded at `0x06000000`.
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- `hardware/generated/asic-rocket-soc/`: FIRRTL, DTS, memory map.
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- `hardware/generated/asic-rocket-soc-verilog/`: synthesis-style split SystemVerilog.
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- `hardware/generated/asic-rocket-soc-sim-verilog/`: simulation split SystemVerilog with init blocks.
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- `targets/asic/rocket/out/generated/asic_rocket_top.sv`: generic ASIC top.
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- `targets/asic/rocket/out/generated/asic_rocket_top_sim.sv`: generic ASIC top for simulation RTL.
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- `targets/asic/rocket/out/filelists/asic_rtl.f`: RTL compile filelist.
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- `targets/asic/rocket/out/filelists/asic_tb.f`: RTL + SimJTAG + models + testbench filelist.
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- `hardware/sim/asic/rocket/tb/`: ASIC testbench and behavioral models.
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The ASIC config is `freechips.rocketchip.fpga.VCU118RocketJtagConfig`; it uses
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JTAG debug export so the testbench can instantiate `SimJTAG`.
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`rtl` keeps FIRRTL/CIRCT randomization disabled for synthesis-style output.
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`sim-rtl`, `vlog-tb`, and `sim` use deterministic simulation init defines so
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Rocket registers that are intentionally not reset come up as concrete 0/1 values
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instead of propagating RTL `X` values. The UART console model prints decoded UART
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characters to the simulator transcript.
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The flash image path can be overridden at simulation runtime with:
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```sh
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+flash_hex=/path/to/image.hex
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```
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